Dff3 filter added to irc inputs.

[fpga/rpi-motor-control.git] / pmsm-control / rpi_pmsm_control.vhdl

diff --git a/pmsm-control/rpi_pmsm_control.vhdl b/pmsm-control/rpi_pmsm_control.vhdl
index beb4b9cfd2fa1fc291ec6681fad2264996f04961..177029f4b2e35c0ce8ed48a90c55ab6f649afc3f 100644 (file)
--- a/pmsm-control/rpi_pmsm_control.vhdl
+++ b/pmsm-control/rpi_pmsm_control.vhdl
@@ -144,10 +144,17 @@ architecture behavioral of rpi_pmsm_control is
        end component;
        
        --frequency division by 12
-       component divider is
-       port (
-               clk_in: in std_logic;
-               div12: out std_logic
+       component cnt_div is
+       generic (
+               cnt_width_g : natural := 4
+       );
+       port
+       (
+               clk_i     : in std_logic;                               --clk to divide
+               en_i      : in std_logic;                               --enable bit?
+               reset_i   : in std_logic;                               --asynch. reset
+               ratio_i   : in std_logic_vector(cnt_width_g-1 downto 0);--initial value
+               q_out_o   : out std_logic                               --generates puls when counter underflows
        );
        end component;
        
@@ -166,6 +173,14 @@ architecture behavioral of rpi_pmsm_control is
        );
        end component;
        
+       component dff3 is
+       port(
+               clk_i   : in std_logic;
+               d_i     : in std_logic;
+               q_o     : out std_logic
+       );
+       end component;
+       
        
        signal adc_channels: std_logic_vector(71 downto 0);
        signal adc_m_count: std_logic_vector(8 downto 0);
@@ -210,6 +225,10 @@ architecture behavioral of rpi_pmsm_control is
        -- irc signals processing
        signal irc_i_prev: std_logic;
        
+       --filetered irc signals
+       signal irc_a_dff3: std_logic;
+       signal irc_b_dff3: std_logic;
+       
        --  attribute syn_noprune of gpio2 : signal is true;
        --  attribute syn_preserve of gpio2 : signal is true;
        --  attribute syn_keep of gpio2 : signal is true;
@@ -243,8 +262,8 @@ begin
        port map (
                clock => gpio_clk,
                reset => '0',
-               a0 => irc_a,
-               b0 => irc_b,
+               a0 => irc_a_dff3,
+               b0 => irc_b_dff3,
                qcount => position,
                a_rise => open,
                a_fall => open,
@@ -278,11 +297,13 @@ begin
        end generate;
        
        
-       div12_map: divider
+       div12_map: cnt_div
        port map(
-               --reset => income_data_valid,
-               clk_in => gpio_clk,
-               div12 => clk_4M17
+               clk_i  => gpio_clk,
+               en_i   =>'1',
+               reset_i   =>'0',
+               ratio_i   =>"1101", --POZN.: counter detekuje cnt<=1
+               q_out_o   =>clk_4M17
        );
        
        -- ADC needs 3.2 MHz clk when powered from +5V Vcc
@@ -302,6 +323,20 @@ begin
                measur_count => adc_m_count
                
        );
+       
+       dff3_a: dff3
+       port map(       
+               clk_i => gpio_clk,
+               d_i   => irc_a,
+               q_o   => irc_a_dff3 
+       );
+       
+       dff3_b: dff3
+       port map(       
+               clk_i => gpio_clk,
+               d_i   => irc_b,
+               q_o   => irc_b_dff3 
+       );
 
        dummy_unused <= gpio2 and gpio3 and
                gpio5 and gpio6 and