);
end component;
- signal spiclk_old_lvl: std_logic :='0'; --pro detekci hrany SPI hodin
+ signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin
signal pwm_in, pwm_dir_in: std_logic;
signal spi_clk: std_logic;
signal gpio_clk: std_logic;
- signal dat_reg : STD_LOGIC_VECTOR (7 downto 0):="10101010";
- --"0000000100100011010001010110011110001001101010111100110111101111";
- --(others=>'0'); --registr pro SPI
+ signal dat_reg : STD_LOGIC_VECTOR (95 downto 0); --shift register for spi
signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
- signal spi_clk_rise: std_logic; --synchronni detekce nabezne hrany spi hodin
- signal spi_clk_fall: std_logic; --synchronni detekce sestupne hrany spi hodin
- signal ce0_int: std_logic;
+ signal ce0_old: std_logic_vector(1 downto 0);
-- attribute syn_noprune of gpio2 : signal is true;
-- attribute syn_preserve of gpio2 : signal is true;
y => gpio_clk
);
- --zesileni signalu CE0
- copyclk3: CLKINT
- port map (
- a => gpio7,
- y => ce0_int
- );
qcount: qcounter
port map (
pwm(3) <= '0';
- process(gpio_clk)
- begin
- if gpio_clk= '1' and gpio_clk'event then
- spiclk_old_lvl<=spi_clk;
- end if;
- end process;
- spi_clk_rise <= (not spiclk_old_lvl) and spi_clk;
- spi_clk_fall <= (not spi_clk) and spiclk_old_lvl;
-
-
- process(spi_clk_fall,spi_clk_rise)
+ process
begin
- if (rising_edge(spi_clk_rise)) then --rising edge, faze cteni
+ --position is obtained on rising edge -> we should write it on falling edge
+ wait until (gpio_clk'event and gpio_clk='0');
+
+ spiclk_old(0)<=spi_clk;
+ spiclk_old(1)<=spiclk_old(0);
+
+ ce0_old(0)<=gpio7;
+ ce0_old(1)<=ce0_old(0);
+
+ if (spiclk_old="01") then --rising edge, faze cteni
if (gpio7 = '0') then -- SPI CS must be selected
-- shift serial data into dat_reg on each rising edge
-- of SCK, MSB first
- dat_reg(7 downto 0) <= dat_reg(6 downto 0) & gpio10;
+ dat_reg(95 downto 0) <= dat_reg(94 downto 0) & gpio10;
end if;
- elsif (rising_edge(spi_clk_fall) ) then --falling edge, faze zapisu
+ elsif (spiclk_old="10" ) then --falling edge, faze zapisu
if (gpio7 = '0') then
- gpio9 <= dat_reg(7); --zapisujeme nejdriv MSB
-
+ gpio9 <= dat_reg(95); --zapisujeme nejdriv MSB
end if;
end if;
+
+
+ --sestupna hrana SS, pripravime data pro prenos-prenos zacina nebo zacatek dalsiho ramce
+ if ((ce0_old = "10") ) then
+ dat_reg(95 downto 64) <= position(31 downto 0); --pozice
+ dat_reg(63 downto 0) <= (others => '1'); --zbytek zatim nuly
+
+ end if;
end process;
+
+
end behavioral;
+