Added ADC reset after each FPGA<->RPi transfer. ADC channels manipulation improved.

[fpga/rpi-motor-control.git] / pmsm-control / rpi_mc_simple_dc.vhdl

diff --git a/pmsm-control/rpi_mc_simple_dc.vhdl b/pmsm-control/rpi_mc_simple_dc.vhdl
index d3f69bceb7bb6b0c52a0eb80633edccdaa0de5bf..1e06af923d5c14d9c8e8a32111afc01c16d406b8 100644 (file)
--- a/pmsm-control/rpi_mc_simple_dc.vhdl
+++ b/pmsm-control/rpi_mc_simple_dc.vhdl
@@ -14,75 +14,77 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use work.util.all;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use work.util.all;

-use work.qcounter.all;

 
 entity rpi_mc_simple_dc is
 
 entity rpi_mc_simple_dc is

-       port (
-               gpio2: in std_logic; -- SDA
-               gpio3: in std_logic; -- SCL
-               gpio4: out std_logic; -- CLK
-               gpio14: in std_logic; -- Tx
-               gpio15: in std_logic; -- Rx
-               gpio17: out std_logic; -- RTS
-               gpio18: out std_logic; -- PWM0/PCMCLK
-               gpio27: out std_logic; -- SD1DAT3
-               gpio22: out std_logic; -- SD1CLK
-               gpio23: out std_logic; -- SD1CMD
-               gpio24: out std_logic; -- SD1DAT0
-               gpio10: in std_logic; -- SPI0MOSI
-               gpio9: out std_logic; -- SPI0MISO
-               gpio25: out std_logic; -- SD1DAT1
-               gpio11: in std_logic; -- SPI0SCLK
-               gpio8: in std_logic; -- SPI0CE0
-               gpio7: in std_logic; -- SPI0CE1
-               gpio5: in std_logic; -- GPCLK1
-               gpio6: in std_logic; -- GPCLK2
-               gpio12: in std_logic; -- PWM0
-               gpio13: in std_logic; -- PWM1
-               gpio19: in std_logic; -- PWM1/SPI1MISO/PCMFS
-               gpio16: in std_logic; -- SPI1CE2
-               gpio26: in std_logic; -- SD1DAT2
-               gpio20: in std_logic; -- SPI1MOSI/PCMDIN/GPCLK0
-               gpio21: in std_logic; -- SPI1SCLK/PCMDOUT/GPCLK1
-               --
-               -- PWM
-               -- Each PWM signal has cooresponding shutdown
-               pwm: out std_logic_vector (1 to 3);
-               shdn: out std_logic_vector (1 to 3);
-               -- Fault/power stage status
-               stat: in std_logic_vector (1 to 3);
-               -- HAL inputs
-               hal_in: in std_logic_vector (1 to 3);
-               -- IRC inputs
-               irc_a: in std_logic;
-               irc_b: in std_logic;
-               irc_i: in std_logic;
-               -- Power status
-               power_stat: in std_logic;
-               -- ADC for current
-               adc_miso: in std_logic;
-               adc_mosi: in std_logic;
-               adc_sclk: in std_logic;
-               adc_scs: in std_logic;
-               -- Extarnal SPI
-               ext_miso: in std_logic; --master in slave out
-               ext_mosi: in std_logic; --master out slave in
-               ext_sclk: in std_logic;
-               ext_scs0: in std_logic;
-               ext_scs1: in std_logic;
-               ext_scs2: in std_logic;
-               -- RS-485 Transceiver
-               rs485_rxd: in std_logic;
-               rs485_txd: out std_logic;
-               rs485_dir: out std_logic;
-               -- CAN Transceiver
-               can_rx: in std_logic;
-               can_tx: in std_logic;
-               -- DIP switch
-               dip_sw: in std_logic_vector (1 to 3); --na desce je prohozene cislovanni
-               -- Unused terminal to keep design tools silent
-               dummy_unused : out std_logic
+generic(
+       pwm_width : natural:=11

        );
        );

+port (
+       gpio2: in std_logic; -- SDA
+       gpio3: in std_logic; -- SCL
+       gpio4: in std_logic; -- CLK
+       gpio14: in std_logic; -- Tx
+       gpio15: in std_logic; -- Rx
+       gpio17: in std_logic; -- RTS
+       gpio18: in std_logic; -- PWM0/PCMCLK
+       gpio27: in std_logic; -- SD1DAT3
+       gpio22: in std_logic; -- SD1CLK
+       gpio23: in std_logic; -- SD1CMD
+       gpio24: in std_logic; -- SD1DAT0
+       gpio10: in std_logic; -- SPI0MOSI
+       gpio9: out std_logic; -- SPI0MISO
+       gpio25: in std_logic; -- SD1DAT1
+       gpio11: in std_logic; -- SPI0SCLK
+       gpio8: in std_logic; -- SPI0CE0
+       gpio7: in std_logic; -- SPI0CE1
+       gpio5: in std_logic; -- GPCLK1
+       gpio6: in std_logic; -- GPCLK2
+       gpio12: in std_logic; -- PWM0
+       gpio13: in std_logic; -- PWM1
+       gpio19: in std_logic; -- PWM1/SPI1MISO/PCMFS
+       gpio16: in std_logic; -- SPI1CE2
+       gpio26: in std_logic; -- SD1DAT2
+       gpio20: in std_logic; -- SPI1MOSI/PCMDIN/GPCLK0
+       gpio21: in std_logic; -- SPI1SCLK/PCMDOUT/GPCLK1
+       --
+       -- PWM
+       -- Each PWM signal has cooresponding shutdown
+       pwm: out std_logic_vector (1 to 3);
+       shdn: out std_logic_vector (1 to 3);
+       -- Fault/power stage status
+       stat: in std_logic_vector (1 to 3);
+       -- HAL inputs
+       hal_in: in std_logic_vector (1 to 3);
+       -- IRC inputs
+       irc_a: in std_logic;
+       irc_b: in std_logic;
+       irc_i: in std_logic;
+       -- Power status
+       power_stat: in std_logic;
+       -- ADC for current
+       adc_miso: in std_logic;
+       adc_mosi: out std_logic;
+       adc_sclk: out std_logic;
+       adc_scs: out std_logic;
+       -- Extarnal SPI
+       ext_miso: in std_logic; --master in slave out
+       ext_mosi: in std_logic; --master out slave in
+       ext_sclk: in std_logic;
+       ext_scs0: in std_logic;
+       ext_scs1: in std_logic;
+       ext_scs2: in std_logic;
+       -- RS-485 Transceiver
+       rs485_rxd: in std_logic;
+       rs485_txd: out std_logic;
+       rs485_dir: out std_logic;
+       -- CAN Transceiver
+       can_rx: in std_logic;
+       can_tx: in std_logic;
+       -- DIP switch
+       dip_sw: in std_logic_vector (1 to 3); --na desce je prohozene cislovanni
+       -- Unused terminal to keep design tools silent
+       dummy_unused : out std_logic
+);

 end rpi_mc_simple_dc;
 
 
 end rpi_mc_simple_dc;
 
 


@@ -102,11 +104,85 @@ architecture behavioral of rpi_mc_simple_dc is
        component CLKINT
                port (A: in std_logic; Y: out std_logic);
        end component;
        component CLKINT
                port (A: in std_logic; Y: out std_logic);
        end component;

+       
+       component qcounter
+       port (
+               clock: in std_logic;
+               reset: in std_logic;
+               a0, b0: in std_logic;
+               qcount: out std_logic_vector (31 downto 0);
+               a_rise, a_fall, b_rise, b_fall, ab_event: out std_logic;
+               ab_error: out std_logic
+       );
+       end component;

 
 

-       signal pwm_in, pwm_dir_in: std_logic;
-       signal spi_clk: std_logic;
-       signal dat_reg : STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); --registr pro SPI
-
+       component mcpwm is
+       generic (
+               pwm_width: natural
+       );
+       port (
+               clock: in std_logic;
+               sync: in std_logic;                             --flag that counter "restarts-overflows"
+               data_valid:in std_logic;                        --indicates data is consistent
+               failsafe: in std_logic;                         --turn off both transistors
+               en_p, en_n: in std_logic;                       --enable positive & enable shutdown
+               match: in std_logic_vector (pwm_width-1 downto 0); --posion of counter when we swap output logic
+               count: in std_logic_vector (pwm_width-1 downto 0); --we use an external counter
+               out_p, out_n: out std_logic                     --pwm outputs: positive & shutdown
+               --TODO add the rest of pwm signals, swap match to pwm_word
+       );
+       end component;
+       
+       component div8 is
+       port (
+               --reset: in std_logic;
+               clk_in: in std_logic;
+               clk_out: out std_logic
+       );
+       end component;
+       
+       component adc_reader is
+       port (
+               clk: in std_logic;                                      --input clk
+               adc_reset: in std_logic;
+               adc_miso: in std_logic;                                 --spi master in slave out
+               adc_channels: out std_logic_vector (35 downto 0);       --consistent data of 3 channels
+               adc_sclk: out std_logic;                                --spi clk
+               adc_scs: out std_logic;                                 --spi slave select
+               adc_mosi: out std_logic                                 --spi master out slave in
+       
+       );
+       end component;
+       
+       
+       signal adc_reset : std_logic;
+       signal adc_channels: std_logic_vector(35 downto 0);
+       
+       signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin
+       --signal pwm_in, pwm_dir_in: std_logic;
+       signal gpio_clk: std_logic;
+       signal dat_reg : STD_LOGIC_VECTOR (95 downto 0); --shift register for spi
+       signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
+       signal ce0_old: std_logic_vector(1 downto 0);
+       
+       --pwm signals
+       constant pwm_n: natural := 3;                                   --number of pwm outputs
+       --number of ticks per pwm cycle, 2^11=2048
+       constant pwm_period : std_logic_vector (pwm_width-1 downto 0) := (others=>'1'); 
+       type pwm_res_type is array(1 to 3) of std_logic_vector (pwm_width-1 downto 0);
+       
+       signal pwm_match: pwm_res_type;                                 --point of reversion of pwm output, 0 to 2047
+       signal pwm_count: std_logic_vector (pwm_width-1 downto 0);      --counter, 0 to 2047
+       signal pwm_sync: std_logic;
+       signal pwm_en_p: std_logic_vector(1 to 3);
+       signal pwm_en_n: std_logic_vector(1 to 3);
+       
+       signal income_data_valid: std_logic;
+       
+       signal clk_3M1: std_logic;
+       
+       
+       

        --  attribute syn_noprune of gpio2 : signal is true;
        --  attribute syn_preserve of gpio2 : signal is true;
        --  attribute syn_keep of gpio2 : signal is true;
        --  attribute syn_noprune of gpio2 : signal is true;
        --  attribute syn_preserve of gpio2 : signal is true;
        --  attribute syn_keep of gpio2 : signal is true;


@@ -114,11 +190,75 @@ architecture behavioral of rpi_mc_simple_dc is
 
 begin
        -- PLL as a reset generator
 
 begin
        -- PLL as a reset generator

-       copyclk: CLKINT
+       
+       --zesileni signalu GPIO CLK
+       copyclk2: CLKINT

        port map (
        port map (

-               a => gpio11,
-               y => spi_clk
+               a => gpio4,
+               y => gpio_clk
+       );
+       
+       
+       qcount: qcounter
+       port map (
+               clock => gpio_clk,
+               reset => '0',
+               a0 => irc_a,
+               b0 => irc_b,
+               qcount => position,
+               a_rise => open,
+               a_fall => open,
+               b_rise => open,
+               b_fall => open,
+               ab_event => open,
+               ab_error => open
+       );
+       
+       pwm_block: for i in pwm_n downto 1 generate
+               pwm_map: mcpwm
+               generic map (
+                       pwm_width => pwm_width
+               )
+               port map (
+                       clock => gpio_clk,                              --50 Mhz clk from gpclk on raspberry
+                       sync => pwm_sync,                               --counter restarts
+                       data_valid => income_data_valid,                        
+                       failsafe => '0',
+                       --
+                       -- pwm config bits & match word
+                       --
+                       en_n => pwm_en_n(i),                            --enable positive pwm
+                       en_p => pwm_en_p(i),                            --enable "negative" ->activate shutdown
+                       match => pwm_match(i),
+                       count => pwm_count,
+                       -- outputs
+                       out_p => pwm(i),                                --positive signal
+                       out_n => shdn(i)                                --reverse signal is in shutdown mode
+               );
+       end generate;
+       
+       
+       div8_map: div8 
+       port map(
+               --reset => income_data_valid,
+               clk_in => gpio_clk,
+               clk_out => clk_3M1

        );
        );

+       
+       adc_reader_map: adc_reader 
+       port map(
+               clk =>clk_3M1,
+               adc_reset => adc_reset,
+               adc_miso => adc_miso,
+               adc_channels => adc_channels,
+               adc_sclk => adc_sclk,
+               adc_scs => adc_scs,
+               adc_mosi => adc_mosi
+               
+       );
+
+       
+       

        --   pll: pll50to200
        --     port map (
        --       powerdown => '1',
        --   pll: pll50to200
        --     port map (
        --       powerdown => '1',


@@ -130,7 +270,7 @@ begin
                                            -- upon power-on
        --   clock <= clkm;
 
                                            -- upon power-on
        --   clock <= clkm;
 

-       dummy_unused <= gpio2 and gpio3  and
+       dummy_unused <= gpio2 and gpio3  and gpio4 and

                gpio5 and gpio6 and
                gpio12 and gpio13 and gpio14 and
                gpio15 and gpio16 and gpio19 and
                gpio5 and gpio6 and
                gpio12 and gpio13 and gpio14 and
                gpio15 and gpio16 and gpio19 and


@@ -138,46 +278,90 @@ begin
                stat(1) and stat(2) and stat(3) and
                hal_in(1) and hal_in(2) and hal_in(3) and
                irc_i and power_stat and 
                stat(1) and stat(2) and stat(3) and
                hal_in(1) and hal_in(2) and hal_in(3) and
                irc_i and power_stat and 

-               adc_miso and adc_mosi and adc_sclk and adc_scs and
+               adc_miso and 

                rs485_rxd and
                can_rx and can_tx and
                dip_sw(1) and dip_sw(2) and dip_sw(3) and
                irc_a and irc_b and
                rs485_rxd and
                can_rx and can_tx and
                dip_sw(1) and dip_sw(2) and dip_sw(3) and
                irc_a and irc_b and

-               -- gpio17 and gpio18 and gpio27 and gpio22 and
+               gpio17 and gpio18 and gpio27 and gpio22 and gpio23 and gpio24 and gpio25 and

                gpio8  and gpio11 and gpio7 and gpio10 and
                ext_scs1 and ext_scs2 and ext_miso and ext_mosi and ext_sclk and ext_scs0;
                        
        rs485_txd <= '1';
        rs485_dir <= '0';
 
                gpio8  and gpio11 and gpio7 and gpio10 and
                ext_scs1 and ext_scs2 and ext_miso and ext_mosi and ext_sclk and ext_scs0;
                        
        rs485_txd <= '1';
        rs485_dir <= '0';
 

- 
-       --gpio24 <= dip_sw(1); --na desce je prohozene cislovani
-
-       shdn(1) <= '0';
-       shdn(2) <= '0';
-       shdn(3) <= '1';

 
 

-       pwm(1) <= '0';
-       pwm(2) <= '0';
-       pwm(3) <= '0';
+       --shdn(1) <= '0';
+       --shdn(2) <= '1';
+       --shdn(3) <= '0';

 
 

-
-  
-       process (spi_clk) --nufunguje preo piny 11,17,27 funguje pro 4,18,22,ext_sclk,10
+       --pwm(1) <= '0';
+       --pwm(2) <= '0';
+       --pwm(3) <= '0';
+       
+       process
+       begin
+               wait until (gpio_clk'event and gpio_clk='1');
+               IF(pwm_count = pwm_period) THEN                         
+               --end of period reached
+                       pwm_count <= (others=>'0');      --reset counter
+                       pwm_sync <= '1';                                -- inform PWM logic about new period start
+               ELSE                                                    --end of period not reached
+                       pwm_count <= std_logic_vector(unsigned(pwm_count)+1);           --increment counter
+                       pwm_sync <= '0';
+               END IF;
+       end process;
+       
+       process

        begin
        begin

-               --if (gpio11'event and gpio11 = '1') then  -- rising edge of SCK
-               if (rising_edge(spi_clk)) then 
+               --position is obtained on rising edge -> we should write it on next cycle
+               wait until (gpio_clk'event and gpio_clk='1');
+               
+               --SCLK edge detection
+               spiclk_old(0)<=gpio11;
+               spiclk_old(1)<=spiclk_old(0);
+               
+               --SS edge detection
+               ce0_old(0)<=gpio7;
+               ce0_old(1)<=ce0_old(0);
+               
+               if (spiclk_old="01") then --rising edge, faze cteni

                        if (gpio7 = '0') then             -- SPI CS must be selected
                                -- shift serial data into dat_reg on each rising edge
                                -- of SCK, MSB first
                        if (gpio7 = '0') then             -- SPI CS must be selected
                                -- shift serial data into dat_reg on each rising edge
                                -- of SCK, MSB first

-                               dat_reg(7 downto 0) <= dat_reg(6 downto 0) & gpio10;
-                
-       
-                       end if;
-               elsif (falling_edge(spi_clk)) then
+                               dat_reg(95 downto 0) <= dat_reg(94 downto 0) & gpio10;
+                               end if;
+               elsif (spiclk_old="10" ) then --falling edge, faze zapisu

                        if (gpio7 = '0') then
                        if (gpio7 = '0') then

-                               gpio9 <= dat_reg(7); --zapisujeme nejdriv MSB
+                               gpio9 <= dat_reg(95); --zapisujeme nejdriv MSB

                        end if;
                end if;
                        end if;
                end if;

+               
+                       
+               --sestupna hrana SS, pripravime data pro prenos
+               if (ce0_old = "10" ) then 
+                       income_data_valid<='0';
+                       dat_reg(95 downto 64) <= position(31 downto 0); --pozice
+                       dat_reg(63 downto 61) <= hal_in(1 to 3); --halovy sondy
+                       dat_reg(60 downto 58) <= pwm_en_p(1 to 3); --enable positive
+                       dat_reg(57 downto 55) <= pwm_en_n(1 to 3); --shutdown
+                       dat_reg(54 downto 49) <= pwm_match(1)(10 downto 5); --6 MSb of PWM1
+                       dat_reg(48 downto 42) <= pwm_match(2)(10 downto 4); --7 MSb of PWM2
+                       dat_reg(41 downto 36) <= pwm_match(3)(10 downto 5); --6 MSb of PWM3
+                       dat_reg(35 downto 0) <= adc_channels(35 downto 0); --current mesurments
+                       adc_reset<='0'; --remove reset flag, and wait on its rising edge
+               elsif (ce0_old = "01") then --rising edge of SS, we should read the data
+                       adc_reset<='1';
+                       pwm_en_p(1 to 3)<=dat_reg(94 downto 92);
+                       pwm_en_n(1 to 3)<=dat_reg(91 downto 89);
+                       --11 bit pwm TODO: make it generic
+                       pwm_match(1)(pwm_width-1 downto 0)<=dat_reg(34 downto 24);
+                       pwm_match(2)(pwm_width-1 downto 0)<=dat_reg(23 downto 13);
+                       -- 12 + 11 Unused
+                       pwm_match(3)(pwm_width-1 downto 0)<=dat_reg(10 downto 0);
+                       income_data_valid<='1';
+               end if;

        end process;
        end process;

+                       

 end behavioral;
 end behavioral;

+