);
end component;
+ component div8 is
+ port (
+ --reset: in std_logic;
+ clk_in: in std_logic;
+ clk_out: out std_logic
+ );
+ end component;
+
type state_type is (f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,f15,r15,reset,rst_wait);
signal state : state_type;
signal income_data_valid: std_logic;
+ signal clk_3M1: std_logic;
+
-- attribute syn_noprune of gpio2 : signal is true;
-- attribute syn_preserve of gpio2 : signal is true;
match => pwm_match(i),
count => pwm_count,
-- outputs
- out_p => pwm(i), --positive signal
- out_n => shdn(i) --reverse signal is in shutdown mode
+ out_p => open,--pwm(i), --positive signal
+ out_n => open--shdn(i) --reverse signal is in shutdown mode
);
end generate;
+ div8_map: div8
+ port map(
+ --reset => income_data_valid,
+ clk_in => gpio_clk,
+ clk_out => clk_3M1
+ );
+
+
-- pll: pll50to200
-- port map (
rs485_dir <= '0';
- --shdn(1) <= '0';
- --shdn(2) <= '0';
- --shdn(3) <= '1';
+ shdn(1) <= '1';
+ shdn(2) <= '1';
+ shdn(3) <= '1';
- --pwm(1) <= '0';
- --pwm(2) <= '0';
- --pwm(3) <= '0';
+ pwm(1) <= '0';
+ pwm(2) <= '0';
+ pwm(3) <= '0';
process
begin
variable reset_re: std_logic:='0';
variable reset_count: integer:=0;
begin
- wait until (gpio_clk'event and gpio_clk='1');
+ wait until (clk_3M1'event and clk_3M1='1');
--reset rising edge detection
adc_rst_old(0)<=adc_reset;