priprava na odesilani pozicez qcounteru - nelze synthetizovat

[fpga/rpi-motor-control.git] / pmsm-control / rpi_mc_simple_dc.vhdl

diff --git a/pmsm-control/rpi_mc_simple_dc.vhdl b/pmsm-control/rpi_mc_simple_dc.vhdl
index d6aa5fe04e121aa31caabace143f32340f48114a..15e8ca6e909e19e07d937b12e00a0d8dd40d6fa0 100644 (file)
--- a/pmsm-control/rpi_mc_simple_dc.vhdl
+++ b/pmsm-control/rpi_mc_simple_dc.vhdl
@@ -14,7 +14,6 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use work.util.all;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use work.util.all;

-use work.qcounter.all;

 
 entity rpi_mc_simple_dc is
 port (
 
 entity rpi_mc_simple_dc is
 port (


@@ -102,13 +101,30 @@ architecture behavioral of rpi_mc_simple_dc is
        component CLKINT
                port (A: in std_logic; Y: out std_logic);
        end component;
        component CLKINT
                port (A: in std_logic; Y: out std_logic);
        end component;

+       
+       component qcounter
+       port (
+               clock: in std_logic;
+               reset: in std_logic;
+               a0, b0: in std_logic;
+               qcount: out std_logic_vector (31 downto 0);
+               a_rise, a_fall, b_rise, b_fall, ab_event: out std_logic;
+               ab_error: out std_logic
+       );
+       end component;

 
        signal spiclk_old_lvl: std_logic :='0'; --pro detekci hrany SPI hodin
        signal pwm_in, pwm_dir_in: std_logic;
        signal spi_clk: std_logic;
        signal gpio_clk: std_logic;
 
        signal spiclk_old_lvl: std_logic :='0'; --pro detekci hrany SPI hodin
        signal pwm_in, pwm_dir_in: std_logic;
        signal spi_clk: std_logic;
        signal gpio_clk: std_logic;

-       signal dat_reg : STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); --registr pro SPI
-
+       signal dat_reg : STD_LOGIC_VECTOR (64 downto 0):=(others=>'0'); --inicializace - funguje?
+       --"0000000100100011010001010110011110001001101010111100110111101111";
+               --(others=>'0'); --registr pro SPI
+       signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
+       --signal spi_clk_rise: std_logic; --synchronni detekce nabezne hrany spi hodin
+       --signal spi_clk_fall: std_logic; --synchronni detekce sestupne hrany spi hodin
+       signal ce0_old: std_logic;
+       

        --  attribute syn_noprune of gpio2 : signal is true;
        --  attribute syn_preserve of gpio2 : signal is true;
        --  attribute syn_keep of gpio2 : signal is true;
        --  attribute syn_noprune of gpio2 : signal is true;
        --  attribute syn_preserve of gpio2 : signal is true;
        --  attribute syn_keep of gpio2 : signal is true;


@@ -131,6 +147,23 @@ begin
                y => gpio_clk
        );
        
                y => gpio_clk
        );
        

+       
+       qcount: qcounter
+       port map (
+               clock => gpio_clk,
+               reset => '0',
+               a0 => irc_a,
+               b0 => irc_b,
+               qcount => position,
+               a_rise => open,
+               a_fall => open,
+               b_rise => open,
+               b_fall => open,
+               ab_event => open,
+               ab_error => open
+       );
+       
+       

        --   pll: pll50to200
        --     port map (
        --       powerdown => '1',
        --   pll: pll50to200
        --     port map (
        --       powerdown => '1',


@@ -162,8 +195,6 @@ begin
        rs485_txd <= '1';
        rs485_dir <= '0';
 
        rs485_txd <= '1';
        rs485_dir <= '0';
 

- 
-       --gpio24 <= dip_sw(1); --na desce je prohozene cislovani

 
        shdn(1) <= '0';
        shdn(2) <= '0';
 
        shdn(1) <= '0';
        shdn(2) <= '0';


@@ -173,24 +204,44 @@ begin
        pwm(2) <= '0';
        pwm(3) <= '0';
 
        pwm(2) <= '0';
        pwm(3) <= '0';
 

-
+       
+--     process(gpio_clk)
+--     begin
+--             if gpio_clk= '1' and gpio_clk'event then
+--                     spiclk_old_lvl<=spi_clk;
+--             end if;
+--     end process;
+--     spi_clk_rise <= (not spiclk_old_lvl) and spi_clk;
+--     spi_clk_fall <= (not spi_clk) and spiclk_old_lvl; 
+ 

   
   

-       process (gpio_clk) 
+--     process(spi_clk_fall,spi_clk_rise)
+       process

        begin
        begin

-               --if (gpio11'event and gpio11 = '1') then  -- rising edge of SCK
-               if ((spi_clk = '1') and (spiclk_old_lvl = '0') ) then 
+               wait until (gpio_clk'event and gpio_clk='1');
+               if (spi_clk='1' and spiclk_old_lvl='0') then --rising edge, faze cteni

                        if (gpio7 = '0') then             -- SPI CS must be selected
                                -- shift serial data into dat_reg on each rising edge
                                -- of SCK, MSB first
                        if (gpio7 = '0') then             -- SPI CS must be selected
                                -- shift serial data into dat_reg on each rising edge
                                -- of SCK, MSB first

-                               dat_reg(7 downto 0) <= dat_reg(6 downto 0) & gpio10;
+                               dat_reg(63 downto 0) <= dat_reg(62 downto 0) & gpio10;

                                spiclk_old_lvl <= '1';
                                spiclk_old_lvl <= '1';

-       
-                       end if;
-               elsif ((spi_clk = '0') and (spiclk_old_lvl = '1')) then
+                               end if;
+               elsif (spi_clk='0' and spiclk_old_lvl='1' ) then --falling edge, faze zapisu

                        if (gpio7 = '0') then
                        if (gpio7 = '0') then

-                               gpio9 <= dat_reg(7); --zapisujeme nejdriv MSB
+                               gpio9 <= dat_reg(63); --zapisujeme nejdriv MSB

                                spiclk_old_lvl <= '0';
                        end if;
                end if;
                                spiclk_old_lvl <= '0';
                        end if;
                end if;

+               
+               if (gpio7='1' and ce0_old = '0') then --nastupna hrana slave select
+                       ce0_old <= '1';
+               elsif (gpio7='0' and ce0_old = '1') then --sestupna hrana SS, pripravime data pro prenos
+                       dat_reg(63 downto 32) <= position(31 downto 0); --pozice
+                       dat_reg(31 downto 0) <= (others => '0'); --zbytek zatim nuly
+                       ce0_old <= '0';
+               end if;

        end process;
        end process;

+       
+               

 end behavioral;
 end behavioral;

+