Unused CLKINT for SCLK removed.

[fpga/rpi-motor-control.git] / pmsm-control / rpi_mc_simple_dc.vhdl

diff --git a/pmsm-control/rpi_mc_simple_dc.vhdl b/pmsm-control/rpi_mc_simple_dc.vhdl
index d6aa5fe04e121aa31caabace143f32340f48114a..6b5dd4bdf001a67b5a9093830975796ea24af32f 100644 (file)
--- a/pmsm-control/rpi_mc_simple_dc.vhdl
+++ b/pmsm-control/rpi_mc_simple_dc.vhdl
@@ -14,7 +14,6 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use work.util.all;
-use work.qcounter.all;
 
 entity rpi_mc_simple_dc is
 port (
@@ -102,13 +101,25 @@ architecture behavioral of rpi_mc_simple_dc is
        component CLKINT
                port (A: in std_logic; Y: out std_logic);
        end component;
+       
+       component qcounter
+       port (
+               clock: in std_logic;
+               reset: in std_logic;
+               a0, b0: in std_logic;
+               qcount: out std_logic_vector (31 downto 0);
+               a_rise, a_fall, b_rise, b_fall, ab_event: out std_logic;
+               ab_error: out std_logic
+       );
+       end component;
 
-       signal spiclk_old_lvl: std_logic :='0'; --pro detekci hrany SPI hodin
+       signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin
        signal pwm_in, pwm_dir_in: std_logic;
-       signal spi_clk: std_logic;
        signal gpio_clk: std_logic;
-       signal dat_reg : STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); --registr pro SPI
-
+       signal dat_reg : STD_LOGIC_VECTOR (95 downto 0); --shift register for spi
+       signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
+       signal ce0_old: std_logic_vector(1 downto 0);
+       
        --  attribute syn_noprune of gpio2 : signal is true;
        --  attribute syn_preserve of gpio2 : signal is true;
        --  attribute syn_keep of gpio2 : signal is true;
@@ -117,13 +128,6 @@ architecture behavioral of rpi_mc_simple_dc is
 begin
        -- PLL as a reset generator
        
-       --zesileni signalu hodin SPI - bez zesileni nelze syntetizovat
-       copyclk: CLKINT
-       port map (
-               a => gpio11,
-               y => spi_clk
-       );
-       
        --zesileni signalu GPIO CLK
        copyclk2: CLKINT
        port map (
@@ -131,6 +135,23 @@ begin
                y => gpio_clk
        );
        
+       
+       qcount: qcounter
+       port map (
+               clock => gpio_clk,
+               reset => '0',
+               a0 => irc_a,
+               b0 => irc_b,
+               qcount => position,
+               a_rise => open,
+               a_fall => open,
+               b_rise => open,
+               b_fall => open,
+               ab_event => open,
+               ab_error => open
+       );
+       
+       
        --   pll: pll50to200
        --     port map (
        --       powerdown => '1',
@@ -162,8 +183,6 @@ begin
        rs485_txd <= '1';
        rs485_dir <= '0';
 
- 
-       --gpio24 <= dip_sw(1); --na desce je prohozene cislovani
 
        shdn(1) <= '0';
        shdn(2) <= '0';
@@ -173,24 +192,41 @@ begin
        pwm(2) <= '0';
        pwm(3) <= '0';
 
-
-  
-       process (gpio_clk) 
+       
+       process
        begin
-               --if (gpio11'event and gpio11 = '1') then  -- rising edge of SCK
-               if ((spi_clk = '1') and (spiclk_old_lvl = '0') ) then 
+               --position is obtained on rising edge -> we should write it on falling edge
+               wait until (gpio_clk'event and gpio_clk='0');
+               
+               --SCLK edge detection
+               spiclk_old(0)<=gpio11;
+               spiclk_old(1)<=spiclk_old(0);
+               
+               --SS edge detection
+               ce0_old(0)<=gpio7;
+               ce0_old(1)<=ce0_old(0);
+               
+               if (spiclk_old="01") then --rising edge, faze cteni
                        if (gpio7 = '0') then             -- SPI CS must be selected
                                -- shift serial data into dat_reg on each rising edge
                                -- of SCK, MSB first
-                               dat_reg(7 downto 0) <= dat_reg(6 downto 0) & gpio10;
-                               spiclk_old_lvl <= '1';
-       
-                       end if;
-               elsif ((spi_clk = '0') and (spiclk_old_lvl = '1')) then
+                               dat_reg(95 downto 0) <= dat_reg(94 downto 0) & gpio10;
+                               end if;
+               elsif (spiclk_old="10" ) then --falling edge, faze zapisu
                        if (gpio7 = '0') then
-                               gpio9 <= dat_reg(7); --zapisujeme nejdriv MSB
-                               spiclk_old_lvl <= '0';
+                               gpio9 <= dat_reg(95); --zapisujeme nejdriv MSB
                        end if;
                end if;
+               
+                       
+               --sestupna hrana SS, pripravime data pro prenos-prenos zacina nebo zacatek dalsiho ramce
+               if ((ce0_old = "10") ) then 
+                       dat_reg(95 downto 64) <= position(31 downto 0); --pozice
+                       dat_reg(63 downto 0) <= (others => '1'); --zbytek zatim nuly
+
+               end if;
        end process;
+       
+               
 end behavioral;
+