+
+ case state is
+ when reset=>
+ reset_re:='0'; --clear reset flag
+ adc_scs<='1'; --active-low SS
+ adc_sclk<='0'; --lower clock
+ data_ready:='0';
+ --addresse are CH(A2,A1,A0): CH0:(0,0,1),CH1:(1,0,1),CH2:(0,1,0)
+ adc_address<="001101010";
+ channel:=ch0;
+ adc_channels(35 downto 0)<=(others=>'1'); --for debug only - remove this line!
+ adc_data(11 downto 0)<=(others=>'1');
+ reset_count:=0;
+ state<=rst_wait;
+ when rst_wait=>
+ if (reset_count<10) then
+ reset_count:=reset_count+1;
+ if (reset_count=7) then
+ adc_scs<='0'; --give the adc some time to prepare before trensfer
+ end if;
+ else
+ state<=f1;
+ end if;
+ when f1=> --1st 'fallin edge' - its not falling edge in any case-if rst clock is low before
+ adc_sclk<='0'; --clk
+ adc_mosi<='1'; --start bit
+ state<=r1; --next state
+ when r1=> --1st rising edge (adc gets the start bit, we get date..)
+ adc_sclk<='1';
+ adc_data(5)<=adc_miso;
+ state<=f2;
+ when f2=> --2nd falling edge
+ adc_sclk<='0';
+ adc_mosi<=adc_address(8); --A2 address
+ state<=r2;
+ when r2=> --2nd rising edge (adc gets A2 address)
+ adc_sclk<='1';
+ adc_data(4)<=adc_miso;
+ state<=f3;
+ when f3=> --3rd falling edge
+ adc_sclk<='0';
+ adc_mosi<=adc_address(7); --A1 address
+ state<=r3;
+ when r3=> --rising edge
+ adc_sclk<='1';
+ adc_data(3)<=adc_miso;
+ state<=f4;
+ when f4=> --4th falling edge
+ adc_sclk<='0';
+ adc_mosi<=adc_address(6); --A0 address
+ --shift the addresses
+ adc_address(8 downto 0)<=adc_address(5 downto 0) & adc_address(8 downto 6);
+ state<=r4;
+ when r4=> --rising edge
+ adc_sclk<='1';
+ adc_data(2)<=adc_miso;
+ state<=f5;
+ when f5=> --5th falling edge
+ adc_sclk<='0';
+ adc_mosi<='0'; --MODE (LOW -12bit)
+ state<=r5;
+ when r5=> --rising edge
+ adc_sclk<='1';
+ adc_data(1)<=adc_miso;
+ state<=f6;
+ when f6=> --6th falling edge
+ adc_sclk<='0';
+ adc_mosi<='1'; --SGL/DIF (HIGH - SGL=Single Ended)
+ state<=r6;
+ when r6=> --6th rising edge (we read last bit of conversion, adc gets SGL/DIF)
+ adc_sclk<='1';
+ adc_data(0)<=adc_miso;
+ state<=f7;
+ when f7=> -- 7th falling edge
+ adc_sclk<='0';
+ adc_mosi<='0'; --PD1 (power down - PD1=PD0=0 -> power down between conversion)
+ state<=r7;
+ when r7=> --7th rising edge, data ready
+ adc_sclk<='1';
+ if (data_ready='1') then
+ case channel is
+ when ch0=>
+ adc_channels(35 downto 24)<=adc_data(11 downto 0);
+ --adc_channels(35 downto 24)<=(others=>'0');
+ channel:=ch1;
+ when ch1=>
+ adc_channels(23 downto 12)<=adc_data(11 downto 0);
+ --adc_channels(23 downto 12)<=(others=>'1');
+ channel:=ch2;
+ when ch2=>
+ adc_channels(11 downto 0)<=adc_data(11 downto 0);
+ --adc_channels(11 downto 0)<=(others=>'0');
+ channel:=ch0;
+ end case;
+ end if;
+ data_ready:='1';
+ state<=f8;
+ when f8=> --8th falling edge
+ adc_sclk<='0';
+ adc_mosi<='0'; --PD0
+ state<=r8;
+ when r8=> --8th rising edge (adc gets PD0)
+ adc_sclk<='1';
+ state<=f9;
+ when f9=> --9th falling edge busy state between conversion (we write nothing)
+ adc_sclk<='0';
+ state<=r9;
+ when r9=> --9th rising edge (we nor ads get nothing)
+ adc_sclk<='1';
+ state<=f10;
+ when f10=> --10th falling edge
+ adc_sclk<='0';
+ state<=r10;
+ when r10=> --10th rising edge (we read 1. bit of conversion)
+ adc_sclk<='1';
+ adc_data(11)<=adc_miso;
+ state<=f11;
+ when f11=>
+ adc_sclk<='0';
+ state<=r11;
+ when r11=> --11th rising edge
+ adc_sclk<='1';
+ adc_data(10)<=adc_miso;
+ state<=f12;
+ when f12=>
+ adc_sclk<='0';
+ state<=r12;
+ when r12=> --12th rising edge
+ adc_sclk<='1';
+ adc_data(9)<=adc_miso;
+ state<=f13;
+ when f13=>
+ adc_sclk<='0';
+ state<=r13;
+ when r13=> --13th rising edge
+ adc_sclk<='1';
+ adc_data(8)<=adc_miso;
+ state<=f14;
+ when f14=>
+ adc_sclk<='0';
+ state<=r14;
+ when r14=> --14th rising edge
+ adc_sclk<='1';
+ adc_data(7)<=adc_miso;
+ state<=f15;
+ when f15=>
+ adc_sclk<='0';
+ --for rising edge detection in next cycle
+ state<=r15;
+ when r15=> --15th rising edge
+ adc_sclk<='1';
+ adc_data(6)<=adc_miso;
+ if (reset_re='1') then --we check rising edge of reset
+ state<=reset;
+ else
+ state<=f1;
+ end if;
+ end case;