power_stat: in std_logic;
-- ADC for current
adc_miso: in std_logic;
- adc_mosi: in std_logic;
- adc_sclk: in std_logic;
- adc_scs: in std_logic;
+ adc_mosi: out std_logic;
+ adc_sclk: out std_logic;
+ adc_scs: out std_logic;
-- Extarnal SPI
ext_miso: in std_logic; --master in slave out
ext_mosi: in std_logic; --master out slave in
);
end component;
- signal spiclk_old_lvl: std_logic :='0'; --pro detekci hrany SPI hodin
+ type state_type is (f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,f15,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15);
+ signal state : state_type;
+ signal adc_data: std_logic_vector(11 downto 0); --ADC income data
+
+ signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin
signal pwm_in, pwm_dir_in: std_logic;
- signal spi_clk: std_logic;
signal gpio_clk: std_logic;
- signal dat_reg : STD_LOGIC_VECTOR (64 downto 0):=(others=>'0'); --inicializace - funguje?
- --"0000000100100011010001010110011110001001101010111100110111101111";
- --(others=>'0'); --registr pro SPI
+ signal dat_reg : STD_LOGIC_VECTOR (95 downto 0); --shift register for spi
signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
- --signal spi_clk_rise: std_logic; --synchronni detekce nabezne hrany spi hodin
- --signal spi_clk_fall: std_logic; --synchronni detekce sestupne hrany spi hodin
- signal ce0_old: std_logic;
+ signal ce0_old: std_logic_vector(1 downto 0);
+
+
-- attribute syn_noprune of gpio2 : signal is true;
-- attribute syn_preserve of gpio2 : signal is true;
begin
-- PLL as a reset generator
- --zesileni signalu hodin SPI - bez zesileni nelze syntetizovat
- copyclk: CLKINT
- port map (
- a => gpio11,
- y => spi_clk
- );
-
--zesileni signalu GPIO CLK
copyclk2: CLKINT
port map (
stat(1) and stat(2) and stat(3) and
hal_in(1) and hal_in(2) and hal_in(3) and
irc_i and power_stat and
- adc_miso and adc_mosi and adc_sclk and adc_scs and
+ adc_miso and
rs485_rxd and
can_rx and can_tx and
dip_sw(1) and dip_sw(2) and dip_sw(3) and
pwm(3) <= '0';
--- process(gpio_clk)
--- begin
--- if gpio_clk= '1' and gpio_clk'event then
--- spiclk_old_lvl<=spi_clk;
--- end if;
--- end process;
--- spi_clk_rise <= (not spiclk_old_lvl) and spi_clk;
--- spi_clk_fall <= (not spi_clk) and spiclk_old_lvl;
-
-
--- process(spi_clk_fall,spi_clk_rise)
process
begin
+ --position is obtained on rising edge -> we should write it on next cycle
wait until (gpio_clk'event and gpio_clk='1');
- if (spi_clk='1' and spiclk_old_lvl='0') then --rising edge, faze cteni
+
+ --SCLK edge detection
+ spiclk_old(0)<=gpio11;
+ spiclk_old(1)<=spiclk_old(0);
+
+ --SS edge detection
+ ce0_old(0)<=gpio7;
+ ce0_old(1)<=ce0_old(0);
+
+ if (spiclk_old="01") then --rising edge, faze cteni
if (gpio7 = '0') then -- SPI CS must be selected
-- shift serial data into dat_reg on each rising edge
-- of SCK, MSB first
- dat_reg(63 downto 0) <= dat_reg(62 downto 0) & gpio10;
- spiclk_old_lvl <= '1';
+ dat_reg(95 downto 0) <= dat_reg(94 downto 0) & gpio10;
end if;
- elsif (spi_clk='0' and spiclk_old_lvl='1' ) then --falling edge, faze zapisu
+ elsif (spiclk_old="10" ) then --falling edge, faze zapisu
if (gpio7 = '0') then
- gpio9 <= dat_reg(63); --zapisujeme nejdriv MSB
- spiclk_old_lvl <= '0';
+ gpio9 <= dat_reg(95); --zapisujeme nejdriv MSB
end if;
end if;
- if (gpio7='1' and ce0_old = '0') then --nastupna hrana slave select
- ce0_old <= '1';
- elsif (gpio7='0' and ce0_old = '1') then --sestupna hrana SS, pripravime data pro prenos
- dat_reg(63 downto 32) <= position(31 downto 0); --pozice
- dat_reg(31 downto 0) <= (others => '0'); --zbytek zatim nuly
- ce0_old <= '0';
+
+ --sestupna hrana SS, pripravime data pro prenos
+ if ((ce0_old = "10") ) then
+ dat_reg(95 downto 64) <= position(31 downto 0); --pozice
+ dat_reg(63 downto 61) <= hal_in(1 to 3); --halovy sondy
+ dat_reg(60 downto 0) <= (others => '1'); --zbytek zatim nuly
+
end if;
end process;
+ process
+ begin
+ wait until (gpio_clk'event and gpio_clk='1');
+ case state is
+ when f1=>
+ adc_sclk<='0'; --clk
+ adc_scs<='0'; --active-high SS
+ adc_mosi<='1'; --start bit
+ state<=r1; --next state
+ when r1=> --rising edge
+ adc_sclk<='1';
+ adc_data(5)<=adc_miso;
+ state<=f2;
+ when f2=> --2nd falling edge
+ adc_sclk<='0';
+ adc_mosi<='0'; --A2 address
+ state<=r2;
+ when r2=> --rising edge
+ adc_sclk<='1';
+ adc_data(4)<=adc_miso;
+ state<=f3;
+ when f3=> --3rd falling edge
+ adc_sclk<='0';
+ adc_mosi<='0'; --A1 address
+ state<=r3;
+ when r3=> --rising edge
+ adc_sclk<='1';
+ adc_data(3)<=adc_miso;
+ state<=f4;
+ when f4=> --4th falling edge
+ adc_sclk<='0';
+ adc_mosi<='1'; --A0 address
+ state<=r4;
+ when r4=> --rising edge
+ adc_sclk<='1';
+ adc_data(2)<=adc_miso;
+ state<=f5;
+ when f5=> --5th falling edge
+ adc_sclk<='0';
+ adc_mosi<='0'; --MODE (LOW -12bit)
+ state<=r5;
+ when r5=> --rising edge
+ adc_sclk<='1';
+ adc_data(1)<=adc_miso;
+ state<=f6;
+ when f6=> --6th falling edge
+ adc_sclk<='0';
+ adc_mosi<='1'; --SGL/DIF (HIGH - SGL=Single Ended)
+ state<=r6;
+ when r6=> --rising edge
+ adc_sclk<='1';
+ adc_data(0)<=adc_miso;
+ state<=f7;
+ when f7=> -- 7th falling edge
+ adc_sclk<='0';
+ adc_mosi<='0'; --PD1 (power down - PD1=PD0=0 -> power down between conversion)
+ state<=r7;
+ when r7=> --rising edge, data ready
+ adc_sclk<='1';
+ state<=f8;
+ when f8=> --8th falling edge
+ adc_sclk<='0';
+ adc_mosi<='0'; --PD0
+ state<=r8;
+ when r8=> --rising edge
+ adc_sclk<='1';
+ state<=f9;
+ when f9=> --busy state between conversion, 9th falling edge
+ adc_sclk<='0';
+ state<=r9;
+ when r9=> --10th rising edge
+ adc_sclk<='1';
+ adc_data(11)<=adc_miso;
+ state<=f10;
+ when f10=>
+ adc_sclk<='0';
+ state<=r10;
+ when r10=> --11th rising edge
+ adc_sclk<='1';
+ adc_data(10)<=adc_miso;
+ state<=f11;
+ when f11=>
+ adc_sclk<='0';
+ state<=r11;
+ when r11=> --12th rising edge
+ adc_sclk<='1';
+ adc_data(9)<=adc_miso;
+ state<=f12;
+ when f12=>
+ adc_sclk<='0';
+ state<=r12;
+ when r12=> --13th rising edge
+ adc_sclk<='1';
+ adc_data(8)<=adc_miso;
+ state<=f13;
+ when f13=>
+ adc_sclk<='0';
+ state<=r13;
+ when r13=> --14th rising edge
+ adc_sclk<='1';
+ adc_data(7)<=adc_miso;
+ state<=f14;
+ when f14=>
+ adc_sclk<='0';
+ state<=r14;
+ when r14=> --15th rising edge
+ adc_data(6)<=adc_miso;
+ state<=f1;
+ end case;
+ end process;
+
+
end behavioral;
projects / fpga / rpi-motor-control.git / blobdiff