gpio4: in std_logic; -- CLK
gpio14: in std_logic; -- Tx
gpio15: in std_logic; -- Rx
- gpio17: out std_logic; -- RTS
- gpio18: out std_logic; -- PWM0/PCMCLK
- gpio27: out std_logic; -- SD1DAT3
- gpio22: out std_logic; -- SD1CLK
- gpio23: out std_logic; -- SD1CMD
- gpio24: out std_logic; -- SD1DAT0
+ gpio17: in std_logic; -- RTS
+ gpio18: in std_logic; -- PWM0/PCMCLK
+ gpio27: in std_logic; -- SD1DAT3
+ gpio22: in std_logic; -- SD1CLK
+ gpio23: in std_logic; -- SD1CMD
+ gpio24: in std_logic; -- SD1DAT0
gpio10: in std_logic; -- SPI0MOSI
gpio9: out std_logic; -- SPI0MISO
- gpio25: out std_logic; -- SD1DAT1
+ gpio25: in std_logic; -- SD1DAT1
gpio11: in std_logic; -- SPI0SCLK
gpio8: in std_logic; -- SPI0CE0
gpio7: in std_logic; -- SPI0CE1
);
end component;
- type state_type is (f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,f15,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15);
+ type state_type is (f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,reset);
signal state : state_type;
+
+ type channel_type is (ch0, ch1, ch2);
+
signal adc_data: std_logic_vector(11 downto 0); --ADC income data
+ signal adc_reset : std_logic;
+ signal adc_rst_old : std_logic_vector(1 downto 0);
+ signal adc_address: std_logic_vector(8 downto 0);
+ signal adc_channels: std_logic_vector(35 downto 0);
signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin
- signal pwm_in, pwm_dir_in: std_logic;
+ --signal pwm_in, pwm_dir_in: std_logic;
signal gpio_clk: std_logic;
signal dat_reg : STD_LOGIC_VECTOR (95 downto 0); --shift register for spi
signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
can_rx and can_tx and
dip_sw(1) and dip_sw(2) and dip_sw(3) and
irc_a and irc_b and
- -- gpio17 and gpio18 and gpio27 and gpio22 and
+ gpio17 and gpio18 and gpio27 and gpio22 and gpio23 and gpio24 and gpio25 and
gpio8 and gpio11 and gpio7 and gpio10 and
ext_scs1 and ext_scs2 and ext_miso and ext_mosi and ext_sclk and ext_scs0;
--sestupna hrana SS, pripravime data pro prenos
- if ((ce0_old = "10") ) then
+ if (ce0_old = "10" ) then
dat_reg(95 downto 64) <= position(31 downto 0); --pozice
dat_reg(63 downto 61) <= hal_in(1 to 3); --halovy sondy
- dat_reg(60 downto 0) <= (others => '1'); --zbytek zatim nuly
-
+ dat_reg(60 downto 36) <= (others => '1'); --let the rest fill with ones
+ dat_reg(35 downto 0) <= adc_channels(35 downto 0); --current mesurments
+ adc_reset<='0'; --remove reset flag, and wait on its rising edge
+ elsif (ce0_old = "01") then --rising edge of SS, we should read the data
+ adc_reset<=dat_reg(95);
end if;
end process;
process
+ variable data_ready : std_logic;
+ variable channel: channel_type;
begin
wait until (gpio_clk'event and gpio_clk='1');
case state is
+ when reset=>
+ adc_scs<='1'; --active-high SS
+ data_ready:='0';
+ --addresse are CH(A2,A1,A0): CH0:(0,0,1),CH1:(1,0,1),CH2:(0,1,0)
+ adc_address<="001101010";
+ channel:=ch0;
when f1=>
- adc_sclk<='0'; --clk
adc_scs<='0'; --active-high SS
+ adc_sclk<='0'; --clk
adc_mosi<='1'; --start bit
state<=r1; --next state
when r1=> --rising edge
state<=f2;
when f2=> --2nd falling edge
adc_sclk<='0';
- adc_mosi<='0'; --A2 address
+ adc_mosi<=adc_address(8); --A2 address
state<=r2;
when r2=> --rising edge
adc_sclk<='1';
state<=f3;
when f3=> --3rd falling edge
adc_sclk<='0';
- adc_mosi<='0'; --A1 address
+ adc_mosi<=adc_address(7); --A1 address
state<=r3;
when r3=> --rising edge
adc_sclk<='1';
state<=f4;
when f4=> --4th falling edge
adc_sclk<='0';
- adc_mosi<='1'; --A0 address
+ adc_mosi<=adc_address(6); --A0 address
+ --shift the addresses
+ adc_address(8 downto 0)<=adc_address(5 downto 0) & adc_address(8 downto 6);
state<=r4;
when r4=> --rising edge
adc_sclk<='1';
state<=r7;
when r7=> --rising edge, data ready
adc_sclk<='1';
+ if (data_ready='1') then
+ case channel is
+ when ch0=>
+ --adc_channels(35 downto 24)<=adc_data(11 downto 0);
+ adc_channels(35 downto 24)<=(others=>'0');
+ channel:=ch1;
+ when ch1=>
+ --adc_channels(23 downto 12)<=adc_data(11 downto 0);
+ adc_channels(23 downto 12)<=(others=>'1');
+ channel:=ch2;
+ when ch2=>
+ --adc_channels(11 downto 0)<=adc_data(11 downto 0);
+ adc_channels(11 downto 0)<=(others=>'0');
+ channel:=ch0;
+ end case;
+ end if;
+ data_ready:='1';
state<=f8;
when f8=> --8th falling edge
adc_sclk<='0';
state<=f14;
when f14=>
adc_sclk<='0';
+ --for rising edge detection in next cycle
+ adc_rst_old(0)<=adc_reset;
+ adc_rst_old(1)<=adc_rst_old(0);
state<=r14;
when r14=> --15th rising edge
+ adc_sclk<='1';
adc_data(6)<=adc_miso;
- state<=f1;
+ if (adc_rst_old="01") then --we check rising edge of reset
+ state<=reset;
+ else
+ state<=f1;
+ end if;
end case;
end process;
projects / fpga / rpi-motor-control.git / blobdiff