Unused lines removed.

[fpga/rpi-motor-control.git] / pmsm-control / rpi_mc_simple_dc.vhdl

diff --git a/pmsm-control/rpi_mc_simple_dc.vhdl b/pmsm-control/rpi_mc_simple_dc.vhdl
index f3ca0878739665aac504b59cb77fb185cb0da8a3..c4471187a39ad2605bc816238048cdeac9684b45 100644 (file)
--- a/pmsm-control/rpi_mc_simple_dc.vhdl
+++ b/pmsm-control/rpi_mc_simple_dc.vhdl
@@ -16,72 +16,72 @@ use ieee.numeric_std.all;
 use work.util.all;
 
 entity rpi_mc_simple_dc is
 use work.util.all;
 
 entity rpi_mc_simple_dc is

-       port (
-               gpio2: in std_logic; -- SDA
-               gpio3: in std_logic; -- SCL
-               gpio4: out std_logic; -- CLK
-               gpio14: in std_logic; -- Tx
-               gpio15: in std_logic; -- Rx
-               gpio17: out std_logic; -- RTS
-               gpio18: out std_logic; -- PWM0/PCMCLK
-               gpio27: out std_logic; -- SD1DAT3
-               gpio22: out std_logic; -- SD1CLK
-               gpio23: out std_logic; -- SD1CMD
-               gpio24: out std_logic; -- SD1DAT0
-               gpio10: in std_logic; -- SPI0MOSI
-               gpio9: in std_logic; -- SPI0MISO
-               gpio25: out std_logic; -- SD1DAT1
-               gpio11: in std_logic; -- SPI0SCLK
-               gpio8: in std_logic; -- SPI0CE0
-               gpio7: in std_logic; -- SPI0CE1
-               gpio5: in std_logic; -- GPCLK1
-               gpio6: in std_logic; -- GPCLK2
-               gpio12: in std_logic; -- PWM0
-               gpio13: in std_logic; -- PWM1
-               gpio19: in std_logic; -- PWM1/SPI1MISO/PCMFS
-               gpio16: in std_logic; -- SPI1CE2
-               gpio26: in std_logic; -- SD1DAT2
-               gpio20: in std_logic; -- SPI1MOSI/PCMDIN/GPCLK0
-               gpio21: in std_logic; -- SPI1SCLK/PCMDOUT/GPCLK1
-               --
-               -- PWM
-               -- Each PWM signal has cooresponding shutdown
-               pwm: out std_logic_vector (1 to 3);
-               shdn: out std_logic_vector (1 to 3);
-               -- Fault/power stage status
-               stat: in std_logic_vector (1 to 3);
-               -- HAL inputs
-               hal_in: in std_logic_vector (1 to 3);
-               -- IRC inputs
-               irc_a: in std_logic;
-               irc_b: in std_logic;
-               irc_i: in std_logic;
-               -- Power status
-               power_stat: in std_logic;
-               -- ADC for current
-               adc_miso: in std_logic;
-               adc_mosi: in std_logic;
-               adc_sclk: in std_logic;
-               adc_scs: in std_logic;
-               -- Extarnal SPI
-               ext_miso: in std_logic; --master in slave out
-               ext_mosi: in std_logic; --master out slave in
-               ext_sclk: in std_logic;
-               ext_scs0: in std_logic;
-               ext_scs1: in std_logic;
-               ext_scs2: in std_logic;
-               -- RS-485 Transceiver
-               rs485_rxd: in std_logic;
-               rs485_txd: out std_logic;
-               rs485_dir: out std_logic;
-               -- CAN Transceiver
-               can_rx: in std_logic;
-               can_tx: in std_logic;
-               -- DIP switch
-               dip_sw: in std_logic_vector (1 to 3); --na desce je prohozene cislovanni
-               -- Unused terminal to keep design tools silent
-               dummy_unused : out std_logic
-       );
+port (
+       gpio2: in std_logic; -- SDA
+       gpio3: in std_logic; -- SCL
+       gpio4: in std_logic; -- CLK
+       gpio14: in std_logic; -- Tx
+       gpio15: in std_logic; -- Rx
+       gpio17: out std_logic; -- RTS
+       gpio18: out std_logic; -- PWM0/PCMCLK
+       gpio27: out std_logic; -- SD1DAT3
+       gpio22: out std_logic; -- SD1CLK
+       gpio23: out std_logic; -- SD1CMD
+       gpio24: out std_logic; -- SD1DAT0
+       gpio10: in std_logic; -- SPI0MOSI
+       gpio9: out std_logic; -- SPI0MISO
+       gpio25: out std_logic; -- SD1DAT1
+       gpio11: in std_logic; -- SPI0SCLK
+       gpio8: in std_logic; -- SPI0CE0
+       gpio7: in std_logic; -- SPI0CE1
+       gpio5: in std_logic; -- GPCLK1
+       gpio6: in std_logic; -- GPCLK2
+       gpio12: in std_logic; -- PWM0
+       gpio13: in std_logic; -- PWM1
+       gpio19: in std_logic; -- PWM1/SPI1MISO/PCMFS
+       gpio16: in std_logic; -- SPI1CE2
+       gpio26: in std_logic; -- SD1DAT2
+       gpio20: in std_logic; -- SPI1MOSI/PCMDIN/GPCLK0
+       gpio21: in std_logic; -- SPI1SCLK/PCMDOUT/GPCLK1
+       --
+       -- PWM
+       -- Each PWM signal has cooresponding shutdown
+       pwm: out std_logic_vector (1 to 3);
+       shdn: out std_logic_vector (1 to 3);
+       -- Fault/power stage status
+       stat: in std_logic_vector (1 to 3);
+       -- HAL inputs
+       hal_in: in std_logic_vector (1 to 3);
+       -- IRC inputs
+       irc_a: in std_logic;
+       irc_b: in std_logic;
+       irc_i: in std_logic;
+       -- Power status
+       power_stat: in std_logic;
+       -- ADC for current
+       adc_miso: in std_logic;
+       adc_mosi: in std_logic;
+       adc_sclk: in std_logic;
+       adc_scs: in std_logic;
+       -- Extarnal SPI
+       ext_miso: in std_logic; --master in slave out
+       ext_mosi: in std_logic; --master out slave in
+       ext_sclk: in std_logic;
+       ext_scs0: in std_logic;
+       ext_scs1: in std_logic;
+       ext_scs2: in std_logic;
+       -- RS-485 Transceiver
+       rs485_rxd: in std_logic;
+       rs485_txd: out std_logic;
+       rs485_dir: out std_logic;
+       -- CAN Transceiver
+       can_rx: in std_logic;
+       can_tx: in std_logic;
+       -- DIP switch
+       dip_sw: in std_logic_vector (1 to 3); --na desce je prohozene cislovanni
+       -- Unused terminal to keep design tools silent
+       dummy_unused : out std_logic
+);

 end rpi_mc_simple_dc;
 
 
 end rpi_mc_simple_dc;
 
 


@@ -101,11 +101,26 @@ architecture behavioral of rpi_mc_simple_dc is
        component CLKINT
                port (A: in std_logic; Y: out std_logic);
        end component;
        component CLKINT
                port (A: in std_logic; Y: out std_logic);
        end component;

+       
+       component qcounter
+       port (
+               clock: in std_logic;
+               reset: in std_logic;
+               a0, b0: in std_logic;
+               qcount: out std_logic_vector (31 downto 0);
+               a_rise, a_fall, b_rise, b_fall, ab_event: out std_logic;
+               ab_error: out std_logic
+       );
+       end component;

 
 

+       signal spiclk_old: std_logic_vector(1 downto 0); --pro detekci hrany SPI hodin

        signal pwm_in, pwm_dir_in: std_logic;
        signal spi_clk: std_logic;
        signal pwm_in, pwm_dir_in: std_logic;
        signal spi_clk: std_logic;

-       signal dat_reg : STD_LOGIC_VECTOR (7 downto 0); --registr pro SPI
-
+       signal gpio_clk: std_logic;
+       signal dat_reg : STD_LOGIC_VECTOR (95 downto 0); --shift register for spi
+       signal position: std_logic_vector(31 downto 0); --pozice z qcounteru
+       signal ce0_old: std_logic_vector(1 downto 0);
+       

        --  attribute syn_noprune of gpio2 : signal is true;
        --  attribute syn_preserve of gpio2 : signal is true;
        --  attribute syn_keep of gpio2 : signal is true;
        --  attribute syn_noprune of gpio2 : signal is true;
        --  attribute syn_preserve of gpio2 : signal is true;
        --  attribute syn_keep of gpio2 : signal is true;


@@ -113,11 +128,38 @@ architecture behavioral of rpi_mc_simple_dc is
 
 begin
        -- PLL as a reset generator
 
 begin
        -- PLL as a reset generator

+       
+       --zesileni signalu hodin SPI - bez zesileni nelze syntetizovat

        copyclk: CLKINT
        port map (
                a => gpio11,
                y => spi_clk
        );
        copyclk: CLKINT
        port map (
                a => gpio11,
                y => spi_clk
        );

+       
+       --zesileni signalu GPIO CLK
+       copyclk2: CLKINT
+       port map (
+               a => gpio4,
+               y => gpio_clk
+       );
+       
+       
+       qcount: qcounter
+       port map (
+               clock => gpio_clk,
+               reset => '0',
+               a0 => irc_a,
+               b0 => irc_b,
+               qcount => position,
+               a_rise => open,
+               a_fall => open,
+               b_rise => open,
+               b_fall => open,
+               ab_event => open,
+               ab_error => open
+       );
+       
+       

        --   pll: pll50to200
        --     port map (
        --       powerdown => '1',
        --   pll: pll50to200
        --     port map (
        --       powerdown => '1',


@@ -129,7 +171,7 @@ begin
                                            -- upon power-on
        --   clock <= clkm;
 
                                            -- upon power-on
        --   clock <= clkm;
 

-       dummy_unused <= gpio2 and gpio3  and
+       dummy_unused <= gpio2 and gpio3  and gpio4 and

                gpio5 and gpio6 and
                gpio12 and gpio13 and gpio14 and
                gpio15 and gpio16 and gpio19 and
                gpio5 and gpio6 and
                gpio12 and gpio13 and gpio14 and
                gpio15 and gpio16 and gpio19 and


@@ -143,14 +185,12 @@ begin
                dip_sw(1) and dip_sw(2) and dip_sw(3) and
                irc_a and irc_b and
                -- gpio17 and gpio18 and gpio27 and gpio22 and
                dip_sw(1) and dip_sw(2) and dip_sw(3) and
                irc_a and irc_b and
                -- gpio17 and gpio18 and gpio27 and gpio22 and

-               gpio8 and gpio9 and gpio11 and gpio7 and gpio10 and
+               gpio8  and gpio11 and gpio7 and gpio10 and

                ext_scs1 and ext_scs2 and ext_miso and ext_mosi and ext_sclk and ext_scs0;
                        
        rs485_txd <= '1';
        rs485_dir <= '0';
 
                ext_scs1 and ext_scs2 and ext_miso and ext_mosi and ext_sclk and ext_scs0;
                        
        rs485_txd <= '1';
        rs485_dir <= '0';
 

- 
-       --gpio24 <= dip_sw(1); --na desce je prohozene cislovani

 
        shdn(1) <= '0';
        shdn(2) <= '0';
 
        shdn(1) <= '0';
        shdn(2) <= '0';


@@ -160,27 +200,39 @@ begin
        pwm(2) <= '0';
        pwm(3) <= '0';
 
        pwm(2) <= '0';
        pwm(3) <= '0';
 

-
-  
-       process (spi_clk) --nufunguje preo piny 11,17,27 funguje pro 4,18,22,ext_sclk,10
+       
+       process

        begin
        begin

-               --if (gpio11'event and gpio11 = '1') then  -- rising edge of SCK
-               if (rising_edge(spi_clk)) then 
+               --position is obtained on rising edge -> we should write it on falling edge
+               wait until (gpio_clk'event and gpio_clk='0');
+               
+               spiclk_old(0)<=spi_clk;
+               spiclk_old(1)<=spiclk_old(0);
+               
+               ce0_old(0)<=gpio7;
+               ce0_old(1)<=ce0_old(0);
+               
+               if (spiclk_old="01") then --rising edge, faze cteni

                        if (gpio7 = '0') then             -- SPI CS must be selected
                                -- shift serial data into dat_reg on each rising edge
                                -- of SCK, MSB first
                        if (gpio7 = '0') then             -- SPI CS must be selected
                                -- shift serial data into dat_reg on each rising edge
                                -- of SCK, MSB first

-                               dat_reg(7 downto 0) <= dat_reg(6 downto 0) & gpio10;
-                
-                               gpio4 <= dat_reg(7);
-                               gpio17 <= dat_reg(6);
-                               gpio18 <= dat_reg(5);
-                               gpio27 <= dat_reg(4);
-                               gpio22 <= dat_reg(3);
-                               gpio23 <= dat_reg(2);
-                               gpio24 <= dat_reg(1);
-                               gpio25 <= dat_reg(0);
-       
+                               dat_reg(95 downto 0) <= dat_reg(94 downto 0) & gpio10;
+                               end if;
+               elsif (spiclk_old="10" ) then --falling edge, faze zapisu
+                       if (gpio7 = '0') then
+                               gpio9 <= dat_reg(95); --zapisujeme nejdriv MSB

                        end if;
                end if;
                        end if;
                end if;

+               
+                       
+               --sestupna hrana SS, pripravime data pro prenos-prenos zacina nebo zacatek dalsiho ramce
+               if ((ce0_old = "10") ) then 
+                       dat_reg(95 downto 64) <= position(31 downto 0); --pozice
+                       dat_reg(63 downto 0) <= (others => '1'); --zbytek zatim nuly
+
+               end if;

        end process;
        end process;

+       
+               

 end behavioral;
 end behavioral;

+