# designer SCRIPT:par.tcl LOGFILE:par.log
# create a new design
-new_design -name "rpi_mc_simple_dc" -family "IGLOO"
+new_design -name "rpi_pmsm_control" -family "IGLOO"
set_device \
-die AGL125V5 \
-voltrange COM
# set default back-annotation base-name
-set_defvar "BA_NAME" "rpi_mc_simple_dc_ba"
+set_defvar "BA_NAME" "rpi_pmsm_control_ba"
# set working directory
set_defvar "DESDIR" "par0"
# setup status report options
set_defvar "EXPORT_STATUS_REPORT" "1"
-set_defvar "EXPORT_STATUS_REPORT_FILENAME" "rpi_mc_simple_dc.rpt"
+set_defvar "EXPORT_STATUS_REPORT_FILENAME" "rpi_pmsm_control.rpt"
# legacy audit-mode flags (left here for historical reasons)
set_defvar "AUDIT_NETLIST_FILE" "1"
# import of input files
import_source \
--format "edif" -edif_flavor "GENERIC" -netlist_naming "VHDL" "syn0/rpi_mc_simple_dc.edn" \
+-format "edif" -edif_flavor "GENERIC" -netlist_naming "VHDL" "syn0/rpi_pmsm_control.edn" \
-format "pdc" "rpi_mc_1.pdc"
# export translation of original netlist
-report_high_fanout_nets_limit 10
# auxiliary source files
-import_aux -format "sdc" "syn0/rpi_mc_simple_dc_sdc.sdc"
+import_aux -format "sdc" "syn0/rpi_pmsm_control_sdc.sdc"
-save_design rpi_mc_simple_dc.adb
+save_design rpi_pmsm_control.adb
layout \
-timing_driven \
-route_incremental off \
-placer_high_effort off
-save_design rpi_mc_simple_dc.adb
+save_design rpi_pmsm_control.adb
export \
-format bts_stp \
-feature prog_fpga \
- rpi_mc_simple_dc.stp
+ rpi_pmsm_control.stp
-save_design rpi_mc_simple_dc.adb
+save_design rpi_pmsm_control.adb