use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.util.all;
+use work.qcounter.all;
entity rpi_mc_simple_dc is
port (
-- of SCK, MSB first
dat_reg(7 downto 0) <= dat_reg(6 downto 0) & gpio10;
- gpio4 <= dat_reg(7);
- gpio17 <= dat_reg(6);
- gpio18 <= dat_reg(5);
- gpio27 <= dat_reg(4);
- gpio22 <= dat_reg(3);
- gpio23 <= dat_reg(2);
- gpio24 <= dat_reg(1);
- gpio25 <= dat_reg(0);
end if;
elsif (falling_edge(spi_clk)) then