Added pwm_dump.

This entity controls loading of PWM value form shared memory to the
external PWM component.

diff --git a/pwm_dump.vhd b/pwm_dump.vhd
new file mode 100644 (file)
index 0000000..bf6b8c6
--- /dev/null
+++ b/pwm_dump.vhd
@@ -0,0 +1,82 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+--------------------------------------------------------------------------------
+
+entity pwm_dump is
+  generic (
+    IRF_ADR_W : integer := 5;
+    P_BASE    : integer := 16;
+    PWM_OFF   : integer := 1;
+    PWM_W     : integer := 10);
+  port (
+    -- Primary slave intefrace
+    ACK_O     : out std_logic;
+    CLK_I     : in  std_logic;
+    RST_I     : in  std_logic;
+    STB_I     : in  std_logic;
+    -- PWM interface
+    PWM_DAT_O : out std_logic_vector (PWM_W-1 downto 0);
+    PWM_STB_O : out std_logic;
+    -- Shared dual-port memory
+    IRF_ACK_I : in  std_logic;
+    IRF_ADR_O : out std_logic_vector (IRF_ADR_W-1 downto 0);
+    IRF_DAT_I : in  std_logic_vector (15 downto 0);
+    IRF_STB_O : out std_logic);
+end entity pwm_dump;
+
+--------------------------------------------------------------------------------
+
+architecture behavioral of pwm_dump is
+
+  type state_t is (ready, done);
+  subtype irf_adr_t is std_logic_vector (IRF_ADR_W-1 downto 0);
+
+  constant PWM_ADR : irf_adr_t :=  conv_std_logic_vector(P_BASE + PWM_OFF, IRF_ADR_W);
+  
+  signal state : state_t;
+
+  signal INNER_ACK : std_logic;
+  
+--------------------------------------------------------------------------------
+
+begin
+
+  ACK_O <= STB_I and INNER_ACK;
+
+  PWM_DAT_O <= IRF_DAT_I (PWM_DAT_O'RANGE);
+  
+  IRF_ADR_O <= PWM_ADR;
+  IRF_STB_O <= STB_I;
+
+  
+  FSM : process (CLK_I, RST_I) is
+  begin
+    if RST_I = '1' then
+      state     <= ready;
+      INNER_ACK <= '0';
+      PWM_STB_O <= '0';
+      
+    elsif rising_edge(CLK_I) then
+      case state is
+        when ready =>
+          if STB_I = '1' then
+            state     <= done;
+            INNER_ACK <= '1';
+            PWM_STB_O <= '1';
+          end if;
+
+        when done =>
+          PWM_STB_O <= '0';
+          if STB_I = '0' then
+            state     <= ready;
+            INNER_ACK <= '0';
+          end if;
+      end case;
+    end if;
+  end process;
+  
+end architecture behavioral;
+