+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+--------------------------------------------------------------------------------
+
+entity irc_dump is
+ generic (
+ IRF_ADR_W : integer := 5;
+ IRC_BASE : integer := 1);
+ port (
+ -- Primary slave intefrace
+ ACK_O : out std_logic;
+ CLK_I : in std_logic;
+ RST_I : in std_logic;
+ STB_I : in std_logic;
+ -- IRC interface
+ IRC_DAT_I : in std_logic_vector (15 downto 0);
+ -- Shared dual-port memory
+ IRF_ACK_I : in std_logic;
+ IRF_ADR_O : out std_logic_vector (IRF_ADR_W-1 downto 0);
+ IRF_DAT_O : out std_logic_vector (15 downto 0);
+ IRF_STB_O : out std_logic;
+ IRF_WE_O : out std_logic);
+end entity irc_dump;
+
+--------------------------------------------------------------------------------
+
+architecture behavioral of irc_dump is
+
+ subtype irf_adr_t is std_logic_vector (IRF_ADR_W-1 downto 0);
+
+ constant IRC_ADR : irf_adr_t := conv_std_logic_vector(IRC_BASE, IRF_ADR_W);
+
+ signal INNER_ACK : std_logic;
+
+--------------------------------------------------------------------------------
+
+begin
+
+ ACK_O <= STB_I;
+
+ IRF_DAT_O <= IRC_DAT_I;
+
+ IRF_ADR_O <= IRC_ADR;
+ IRF_STB_O <= STB_I and not INNER_ACK;
+ IRF_WE_O <= STB_I and not INNER_ACK;
+
+
+ process (CLK_I, RST_I) is
+ begin
+ if RST_I = '1' then
+ INNER_ACK <= '0';
+
+ elsif rising_edge(CLK_I) then
+ INNER_ACK <= STB_I;
+ end if;
+ end process;
+
+end architecture behavioral;
+