General counter extended by clk_en input

diff --git a/counter.vhd b/counter.vhd
index 9fe1f7e35737caf3b1c4fae5bfaf21787cb8127d..790d05485fbae44d9d2fa290e269f82242b73e99 100644 (file)
--- a/counter.vhd
+++ b/counter.vhd
@@ -14,6 +14,7 @@ entity counter is
     MAX   : integer);
   port (
     clk      : in  std_logic;
+    clk_en   : in  std_logic;
     reset    : in  std_logic;
     count    : out std_logic_vector (WIDTH-1 downto 0);
     event_ow : out std_logic);
@@ -45,10 +46,12 @@ begin
       cnt <= (others => '0');
 
     elsif rising_edge(clk) then
-      if eq_max = '1' then
-        cnt <= (others => '0');
-      else
-        cnt <= cnt + 1;
+      if clk_en = '1' then
+        if eq_max = '1' then
+          cnt <= (others => '0');
+        else
+          cnt <= cnt + 1;
+        end if;
       end if;
     end if;
   end process;

diff --git a/tb/tb_pwm.vhd b/tb/tb_pwm.vhd
index 3fed912c7dc32d22c671f826de9501ea9955bb24..e77fd47f1434d7d53f8952ed8dfb01756b093e9c 100644 (file)
--- a/tb/tb_pwm.vhd
+++ b/tb/tb_pwm.vhd
@@ -48,6 +48,7 @@ begin
       MAX   => CNT_MAX)
     port map (
       clk      => clk,
+      clk_en   => '1',
       reset    => reset,
       count    => pwm_cnt,
       event_ow => pwm_cyc);