MCC testbench tests all MCC entities/modules.

[fpga/pwm.git] / tb / tb_mcc.vhd

diff --git a/tb/tb_mcc.vhd b/tb/tb_mcc.vhd
index 03d705912ae50a809bf5d839e9fb2d0fec66347f..881ecd635e8d54b8c9bbdb5dfe4488c1e6a8f586 100644 (file)
--- a/tb/tb_mcc.vhd
+++ b/tb/tb_mcc.vhd
@@ -16,7 +16,6 @@ architecture testbench of tb_mcc is
   constant LUT_DAT_W     : integer := 10;
   constant LUT_ADR_W     : integer := 9;
   constant LUT_INIT_FILE : string  := "../sin.lut";
-  constant IRF_ADR_W     : integer := 5;
 
   constant WAVE_SIZE : integer := 2**LUT_ADR_W;
   
@@ -27,7 +26,7 @@ architecture testbench of tb_mcc is
   signal STB_I : std_logic;
 
   signal IRF_ACK_I : std_logic;
-  signal IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
+  signal IRF_ADR_O : std_logic_vector (4 downto 0);
   signal IRF_CYC_O : std_logic;
   signal IRF_DAT_I : std_logic_vector (15 downto 0);
   signal IRF_DAT_O : std_logic_vector (15 downto 0);
@@ -38,11 +37,16 @@ architecture testbench of tb_mcc is
   signal LUT_DAT_I : std_logic_vector (LUT_DAT_W-1 downto 0);
   signal LUT_STB_O : std_logic;
 
+  signal IRC_DAT_I : std_logic_vector (15 downto 0);
+
   
   subtype word_t is std_logic_vector (15 downto 0);
   
-  signal dbg_mem00 : word_t    := "0000000000100100";  -- MCC enable flags (RO)
-  signal dbg_mem04 : word_t    := (others => '0');     -- Angle            (RO)
+  signal dbg_mem00 : word_t    := "0000000000111111";  -- MCC enable flags (RO)
+  signal dbg_mem01 : word_t    := (others => '0');     -- IRC
+  signal dbg_mem02 : word_t    := "0000000000000000";  -- IRC base
+  signal dbg_mem03 : word_t    := "0000000000000111";  -- IRC per revolution (7)
+  signal dbg_mem04 : word_t    := (others => '0');     -- Angle
   signal dbg_mem11 : word_t    := (others => '0');     -- Phase 1
   signal dbg_mem15 : word_t    := (others => '0');     -- Phase 2
   signal dbg_mem19 : word_t    := (others => '0');     -- Phase 3
@@ -55,8 +59,7 @@ begin
   uut : entity work.mcc
     generic map (
       LUT_ADR_W => LUT_ADR_W,
-      LUT_DAT_W => LUT_DAT_W,
-      IRF_ADR_W => IRF_ADR_W)
+      LUT_DAT_W => LUT_DAT_W)
     port map (
       ACK_O      => ACK_O,
       CLK_I      => CLK_I,
@@ -65,7 +68,7 @@ begin
       LUT_STB_O  => LUT_STB_O,
       LUT_ADR_O  => LUT_ADR_O,
       LUT_DAT_I  => LUT_DAT_I,
-      IRC_DAT_I  => (others => '0'),
+      IRC_DAT_I  => IRC_DAT_I,
       PWM_DAT_O  => open,
       PWM1_STB_O => open,
       PWM2_STB_O => open,
@@ -128,6 +131,9 @@ begin
       if IRF_WE_O = '0' then
         case conv_integer(IRF_ADR_O) is
           when 16#00# => IRF_DAT_I <= dbg_mem00;
+          when 16#01# => IRF_DAT_I <= dbg_mem01;
+          when 16#02# => IRF_DAT_I <= dbg_mem02;
+          when 16#03# => IRF_DAT_I <= dbg_mem03;
           when 16#04# => IRF_DAT_I <= dbg_mem04;
           when 16#11# => IRF_DAT_I <= dbg_mem11;
           when 16#15# => IRF_DAT_I <= dbg_mem15;
@@ -136,6 +142,10 @@ begin
         end case;
       else
         case conv_integer(IRF_ADR_O) is
+          when 16#01# => dbg_mem01 <= IRF_DAT_O;
+          when 16#02# => dbg_mem02 <= IRF_DAT_O;
+          when 16#03# => dbg_mem03 <= IRF_DAT_O;
+          when 16#04# => dbg_mem04 <= IRF_DAT_O;
           when 16#11# => dbg_mem11 <= IRF_DAT_O;
           when 16#15# => dbg_mem15 <= IRF_DAT_O;
           when 16#19# => dbg_mem19 <= IRF_DAT_O;
@@ -149,13 +159,14 @@ begin
 
   UUT_FEED : process is
   begin
-    STB_I <= '0';
+    STB_I     <= '0';
         
     wait for offset;
     wait for 4*period;
 
     for i in 0 to 1 loop
-      dbg_mem04 <= conv_std_logic_vector(i, 16);
+      IRC_DAT_I <= conv_std_logic_vector(8*i, 16);
+      --dbg_mem04 <= conv_std_logic_vector(i, 16);     
       
       STB_I <= '1';
       wait until rising_edge(CLK_I) and ACK_O = '1';