FSM : process (CLK_I, RST_I) is
begin
- if RST_I = '1' then
- state <= ready;
- INNER_ACK <= '0';
- PWM_STB_O <= '0';
+ if rising_edge(CLK_I) then
+ if RST_I = '1' then
+ state <= ready;
+ INNER_ACK <= '0';
+ PWM_STB_O <= '0';
- elsif rising_edge(CLK_I) then
- case state is
- when ready =>
- if STB_I = '1' then
- state <= done;
- INNER_ACK <= '1';
- PWM_STB_O <= '1';
- end if;
+ else
+ case state is
+ when ready =>
+ if STB_I = '1' then
+ state <= done;
+ INNER_ACK <= '1';
+ PWM_STB_O <= '1';
+ end if;
- when done =>
- PWM_STB_O <= '0';
- if STB_I = '0' then
- state <= ready;
- INNER_ACK <= '0';
- end if;
- end case;
+ when done =>
+ PWM_STB_O <= '0';
+ if STB_I = '0' then
+ state <= ready;
+ INNER_ACK <= '0';
+ end if;
+ end case;
+ end if;
end if;
end process;