MAX : integer);
port (
clk : in std_logic;
+ clk_en : in std_logic;
reset : in std_logic;
count : out std_logic_vector (WIDTH-1 downto 0);
event_ow : out std_logic);
architecture behavioral of counter is
signal eq_max : std_logic; -- cnt is equal to MAX
- signal cnt : std_logic_vector (WIDTH-1 downto 0);
+ signal cnt : std_logic_vector (WIDTH-1 downto 0) := (others => '0');
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count <= cnt;
- event_ow <= eq_max;
+ event_ow <= eq_max and clk_en;
COUTER : process (clk, reset) is
begin
- if reset = '1' then
- cnt <= (others => '0');
-
- elsif rising_edge(clk) then
- if eq_max = '1' then
+ if rising_edge(clk) then
+ if reset = '1' then
cnt <= (others => '0');
+
else
- cnt <= cnt + 1;
+ if clk_en = '1' then
+ if eq_max = '1' then
+ cnt <= (others => '0');
+ else
+ cnt <= cnt + 1;
+ end if;
+ end if;
end if;
end if;
end process;