Added pwm_min component.

[fpga/pwm.git] / counter.vhd

diff --git a/counter.vhd b/counter.vhd
index 9fe1f7e35737caf3b1c4fae5bfaf21787cb8127d..0994e811f7da1bfd78fe0e81e2f0b81f02560b31 100644 (file)
--- a/counter.vhd
+++ b/counter.vhd
@@ -14,6 +14,7 @@ entity counter is
     MAX   : integer);
   port (
     clk      : in  std_logic;
+    clk_en   : in  std_logic;
     reset    : in  std_logic;
     count    : out std_logic_vector (WIDTH-1 downto 0);
     event_ow : out std_logic);
@@ -24,7 +25,7 @@ end counter;
 architecture behavioral of counter is
 
   signal eq_max : std_logic;            -- cnt is equal to MAX
-  signal cnt    : std_logic_vector (WIDTH-1 downto 0);
+  signal cnt    : std_logic_vector (WIDTH-1 downto 0) := (others => '0');
 
 --------------------------------------------------------------------------------
 
@@ -41,14 +42,18 @@ begin
   
   COUTER : process (clk, reset) is
   begin
-    if reset = '1' then
-      cnt <= (others => '0');
-
-    elsif rising_edge(clk) then
-      if eq_max = '1' then
+    if rising_edge(clk) then
+      if reset = '1' then
         cnt <= (others => '0');
+        
       else
-        cnt <= cnt + 1;
+        if clk_en = '1' then
+          if eq_max = '1' then
+            cnt <= (others => '0');
+          else
+            cnt <= cnt + 1;
+          end if;
+        end if;
       end if;
     end if;
   end process;