Wave_table initialization data format modified.

[fpga/pwm.git] / sequencer.vhd

diff --git a/sequencer.vhd b/sequencer.vhd
index 74733f8034ba0f66e164ebb43f441329e36896b4..d1a0ce9c321d74fecce593311b0cbf7da36c5665 100644 (file)
--- a/sequencer.vhd
+++ b/sequencer.vhd
@@ -21,7 +21,7 @@ entity sequencer is
     -- Slave interface
     SL_ACK_I     : in  std_logic;
     SL_IRF_ADR_I : in  std_logic_vector (IRF_ADR_W-1 downto 0);
-    SL_STB_O     : out std_logic;
+    SL_STB_O     : out std_logic := '0';
     SL_MUX_CODE  : out std_logic_vector (1 downto 0));
 end entity sequencer;
 
@@ -36,9 +36,9 @@ architecture behavioral of sequencer is
   constant P2_MASK: irf_adr_t := conv_std_logic_vector(P_BASE+1*P_SIZE, IRF_ADR_W);
   constant P3_MASK: irf_adr_t := conv_std_logic_vector(P_BASE+2*P_SIZE, IRF_ADR_W);
 
-  signal state     : state_t;
+  signal state     : state_t := ready;
 
-  signal INNER_ACK : std_logic;
+  signal INNER_ACK : std_logic := '0';
 
 --------------------------------------------------------------------------------
 
@@ -60,46 +60,48 @@ begin
 
   FSM : process (CLK_I, RST_I) is
   begin
-    if RST_I = '1' then
-      state     <= ready;
-      INNER_ACK <= '0';
-      SL_STB_O  <= '0';
-
-    elsif rising_edge(CLK_I) then
-      case state is
-        when ready =>
-          if STB_I = '1' then
-            state    <= phase1;
+    if rising_edge(CLK_I) then
+      if RST_I = '1' then
+        state     <= ready;
+        INNER_ACK <= '0';
+        SL_STB_O  <= '0';
+
+      else
+        case state is
+          when ready =>
+            if STB_I = '1' then
+              state    <= phase1;
+              SL_STB_O <= '1';
+            end if;
+
+          when phase1 =>
+            if SL_ACK_I = '1' then
+              state    <= phase2;
+              SL_STB_O <= '0';
+            end if;
+            
+          when phase2 =>
             SL_STB_O <= '1';
-          end if;
-
-        when phase1 =>
-          if SL_ACK_I = '1' then
-            state    <= phase2;
-            SL_STB_O <= '0';
-          end if;
-          
-        when phase2 =>
-          SL_STB_O <= '1';
-          if SL_ACK_I = '1' then
-            state    <= phase3;
-            SL_STB_O <= '0';
-          end if;
-
-        when phase3 =>
-          SL_STB_O <= '1';
-          if SL_ACK_I = '1' then
-            state     <= done;
-            INNER_ACK <= '1';
-            SL_STB_O  <= '0';
-          end if;
-
-        when done =>
-          if STB_I = '0' then
-            state     <= ready;
-            INNER_ACK <= '0';
-          end if;
-      end case;
+            if SL_ACK_I = '1' then
+              state    <= phase3;
+              SL_STB_O <= '0';
+            end if;
+
+          when phase3 =>
+            SL_STB_O <= '1';
+            if SL_ACK_I = '1' then
+              state     <= done;
+              INNER_ACK <= '1';
+              SL_STB_O  <= '0';
+            end if;
+
+          when done =>
+            if STB_I = '0' then
+              state     <= ready;
+              INNER_ACK <= '0';
+            end if;
+        end case;
+      end if;
     end if;
   end process;