entity mcc is
generic (
LUT_ADR_W : integer := 10;
- LUT_DAT_W : integer := 9;
- IRF_ADR_W : integer := 5);
+ LUT_DAT_W : integer := 9);
port (
-- Primary slave intefrace
ACK_O : out std_logic;
PWM3_STB_O : out std_logic;
-- Shared memory interface
IRF_ACK_I : in std_logic;
- IRF_ADR_O : out std_logic_vector (IRF_ADR_W-1 downto 0);
+ IRF_ADR_O : out std_logic_vector (4 downto 0);
IRF_DAT_I : in std_logic_vector (15 downto 0);
IRF_DAT_O : out std_logic_vector (15 downto 0);
IRF_STB_O : out std_logic;
architecture behavioral of mcc is
+ constant IRF_ADR_W : integer := 5;
+
constant MCC_W : integer := 6;
constant MUX_W : integer := 3;
signal SCALE_SL_STB_I : std_logic;
signal PWM_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
- signal PWM_IRF_DAT_O : std_logic_vector (15 downto 0);
signal PWM_IRF_STB_O : std_logic;
--signal PWM_DAT_O : std_logic_vector (LUT_DAT_W-1 downto 0);
signal PWM_STB_O : std_logic;
VECTOR_IRF_ADR_O when MCC_MUX_CODE = 2 else
SCALE_IRF_ADR_O when MCC_MUX_CODE = 3 else
PWM_IRF_ADR_O when MCC_MUX_CODE = 5 else
- (others => '-');
+ (others => 'X');
IRF_DAT_O <= MASTER_IRF_DAT_O when MCC_MUX_EN = '0' else
IRC_IRF_DAT_O when MCC_MUX_CODE = 0 else
BASE_IRF_DAT_O when MCC_MUX_CODE = 1 else
VECTOR_IRF_DAT_O when MCC_MUX_CODE = 2 else
SCALE_IRF_DAT_O when MCC_MUX_CODE = 3 else
- PWM_IRF_DAT_O when MCC_MUX_CODE = 5 else
- (others => '-');
+ (others => 'X');
IRF_STB_O <= MASTER_IRF_STB_O when MCC_MUX_EN = '0' else
IRC_IRF_STB_O when MCC_MUX_CODE = 0 else
PWM2_STB_O <= PWM_STB_O when PWM_SL_MUX_CODE = 1 else '0';
PWM3_STB_O <= PWM_STB_O when PWM_SL_MUX_CODE = 2 else '0';
+ MCC_ACK (4) <= '1';
+
mcc_master_1 : entity work.mcc_master
generic map (