PWM selection signal added.

[fpga/pwm.git] / counter.vhd

diff --git a/counter.vhd b/counter.vhd
index 790d05485fbae44d9d2fa290e269f82242b73e99..9df0e2b86714c49dd95aa37bf1b3455f762e15cf 100644 (file)
--- a/counter.vhd
+++ b/counter.vhd
@@ -25,7 +25,7 @@ end counter;
 architecture behavioral of counter is
 
   signal eq_max : std_logic;            -- cnt is equal to MAX
-  signal cnt    : std_logic_vector (WIDTH-1 downto 0);
+  signal cnt    : std_logic_vector (WIDTH-1 downto 0) := (others => '0');
 
 --------------------------------------------------------------------------------
 
@@ -37,20 +37,22 @@ begin
 
   
   count    <= cnt;
-  event_ow <= eq_max;
+  event_ow <= eq_max and clk_en;
 
   
   COUTER : process (clk, reset) is
   begin
-    if reset = '1' then
-      cnt <= (others => '0');
-
-    elsif rising_edge(clk) then
-      if clk_en = '1' then
-        if eq_max = '1' then
-          cnt <= (others => '0');
-        else
-          cnt <= cnt + 1;
+    if rising_edge(clk) then
+      if reset = '1' then
+        cnt <= (others => '0');
+        
+      else
+        if clk_en = '1' then
+          if eq_max = '1' then
+            cnt <= (others => '0');
+          else
+            cnt <= cnt + 1;
+          end if;
         end if;
       end if;
     end if;