]> rtime.felk.cvut.cz Git - fpga/plasma.git/commitdiff
RAM modified and *.bmm added. lightweight
authorVladimir Burian <buriavl2@fel.cvut.cz>
Tue, 15 Feb 2011 17:52:55 +0000 (18:52 +0100)
committerVladimir Burian <buriavl2@fel.cvut.cz>
Tue, 15 Feb 2011 17:52:55 +0000 (18:52 +0100)
RAM is expanded to 16 KB. Template of *.bmm file is added so the content
of memories can be filled with data from *.elf file using data2mem tool.

vhdl/ram_xilinx.bmm [new file with mode: 0644]
vhdl/ram_xilinx.vhd

diff --git a/vhdl/ram_xilinx.bmm b/vhdl/ram_xilinx.bmm
new file mode 100644 (file)
index 0000000..51bf3c9
--- /dev/null
@@ -0,0 +1,30 @@
+// Mapping of BRAMs used by Plasma MIPS
+// in file "ram_xilinx.vhd"
+//
+// Currently 16 KB are mapped.
+//================================================
+// WARNING !!!
+// "???" signs must be replaced by logical path from
+// the top-level desing to the Plasma MIPS instance.
+//
+// E.g. you have top-level with Plasma MIPS instance
+// named "plasma_1". Then "???" => "plasma_1".
+
+ADDRESS_SPACE plasma_ram RAMB16 [0x0000:0x3fff]
+
+  BUS_BLOCK
+      ???/u2_ram/block0.ram_byte3 [31:24];
+      ???/u2_ram/block0.ram_byte2 [23:16];
+      ???/u2_ram/block0.ram_byte1 [15:8];
+      ???/u2_ram/block0.ram_byte0 [7:0];
+  END_BUS_BLOCK;
+
+  BUS_BLOCK
+      ???/u2_ram/block1.ram_byte3 [31:24];
+      ???/u2_ram/block1.ram_byte2 [23:16];
+      ???/u2_ram/block1.ram_byte1 [15:8];
+      ???/u2_ram/block1.ram_byte0 [7:0];
+  END_BUS_BLOCK;
+
+END_ADDRESS_SPACE;
+
index a1f2a035c9f32f581c4010df437413d12188550f..6bfb3cf9b351286173ad9ea771f6a341e1accb22 100644 (file)
@@ -44,7 +44,7 @@ use UNISIM.vcomponents.all;
 entity ram is\r
    generic(memory_type : string := "DEFAULT";\r
            --Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)\r
-           block_count : integer := 1); \r
+           block_count : integer := 2); \r
    port(clk               : in std_logic;\r
         enable            : in std_logic;\r
         write_byte_enable : in std_logic_vector(3 downto 0);\r