1 //----------------------------------------------------------------------------
2 // Copyright (C) 2001 Authors
4 // This source file may be used and distributed without restriction provided
5 // that this copyright statement is not removed from the file and that any
6 // derivative work contains the original copyright notice and the associated
9 // This source file is free software; you can redistribute it and/or modify
10 // it under the terms of the GNU Lesser General Public License as published
11 // by the Free Software Foundation; either version 2.1 of the License, or
12 // (at your option) any later version.
14 // This source is distributed in the hope that it will be useful, but WITHOUT
15 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
17 // License for more details.
19 // You should have received a copy of the GNU Lesser General Public License
20 // along with this source; if not, write to the Free Software Foundation,
21 // Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
23 //----------------------------------------------------------------------------
25 // *File Name: omsp_alu.v
27 // *Module Description:
31 // - Olivier Girard, olgirard@gmail.com
33 //----------------------------------------------------------------------------
35 // $LastChangedBy: olivier.girard $
36 // $LastChangedDate: 2009-12-29 20:10:34 +0100 (Tue, 29 Dec 2009) $
37 //----------------------------------------------------------------------------
38 `include "timescale.v"
39 `include "openMSP430_defines.v"
44 alu_out, // ALU output value
45 alu_out_add, // ALU adder output value
46 alu_stat, // ALU Status {V,N,Z,C}
47 alu_stat_wr, // ALU Status write {V,N,Z,C}
50 dbg_halt_st, // Halt/Run status from CPU
51 exec_cycle, // Instruction execution cycle
52 inst_alu, // ALU control signals
53 inst_bw, // Decoded Inst: byte width
54 inst_jmp, // Decoded Inst: Conditional jump
55 inst_so, // Single-operand arithmetic
56 op_dst, // Destination operand
57 op_src, // Source operand
58 status // R2 Status {V,N,Z,C}
63 output [15:0] alu_out; // ALU output value
64 output [15:0] alu_out_add; // ALU adder output value
65 output [3:0] alu_stat; // ALU Status {V,N,Z,C}
66 output [3:0] alu_stat_wr; // ALU Status write {V,N,Z,C}
70 input dbg_halt_st; // Halt/Run status from CPU
71 input exec_cycle; // Instruction execution cycle
72 input [11:0] inst_alu; // ALU control signals
73 input inst_bw; // Decoded Inst: byte width
74 input [7:0] inst_jmp; // Decoded Inst: Conditional jump
75 input [7:0] inst_so; // Single-operand arithmetic
76 input [15:0] op_dst; // Destination operand
77 input [15:0] op_src; // Source operand
78 input [3:0] status; // R2 Status {V,N,Z,C}
81 //=============================================================================
83 //=============================================================================
85 function [4:0] bcd_add;
93 Z = {1'b0,X}+{1'b0,Y}+C;
94 if (Z<10) bcd_add = Z;
101 //=============================================================================
102 // 2) INSTRUCTION FETCH/DECODE CONTROL STATE MACHINE
103 //=============================================================================
104 // SINGLE-OPERAND ARITHMETIC:
105 //-----------------------------------------------------------------------------
106 // Mnemonic S-Reg, Operation Status bits
109 // RRC dst C->MSB->...LSB->C * * * *
110 // RRA dst MSB->MSB->...LSB->C 0 * * *
111 // SWPB dst Swap bytes - - - -
112 // SXT dst Bit7->Bit8...Bit15 0 * * *
113 // PUSH src SP-2->SP, src->@SP - - - -
114 // CALL dst SP-2->SP, PC+2->@SP, dst->PC - - - -
115 // RETI TOS->SR, SP+2->SP, TOS->PC, SP+2->SP * * * *
117 //-----------------------------------------------------------------------------
118 // TWO-OPERAND ARITHMETIC:
119 //-----------------------------------------------------------------------------
120 // Mnemonic S-Reg, Operation Status bits
123 // MOV src,dst src -> dst - - - -
124 // ADD src,dst src + dst -> dst * * * *
125 // ADDC src,dst src + dst + C -> dst * * * *
126 // SUB src,dst dst + ~src + 1 -> dst * * * *
127 // SUBC src,dst dst + ~src + C -> dst * * * *
128 // CMP src,dst dst + ~src + 1 * * * *
129 // DADD src,dst src + dst + C -> dst (decimaly) * * * *
130 // BIT src,dst src & dst 0 * * *
131 // BIC src,dst ~src & dst -> dst - - - -
132 // BIS src,dst src | dst -> dst - - - -
133 // XOR src,dst src ^ dst -> dst * * * *
134 // AND src,dst src & dst -> dst 0 * * *
136 //-----------------------------------------------------------------------------
137 // * the status bit is affected
138 // - the status bit is not affected
139 // 0 the status bit is cleared
140 // 1 the status bit is set
141 //-----------------------------------------------------------------------------
143 // Invert source for substract and compare instructions.
144 wire op_src_inv_cmd = exec_cycle & (inst_alu[`ALU_SRC_INV]);
145 wire [15:0] op_src_inv = {16{op_src_inv_cmd}} ^ op_src;
148 // Mask the bit 8 for the Byte instructions for correct flags generation
149 wire op_bit8_msk = ~exec_cycle | ~inst_bw;
150 wire [16:0] op_src_in = {1'b0, op_src_inv[15:9], op_src_inv[8] & op_bit8_msk, op_src_inv[7:0]};
151 wire [16:0] op_dst_in = {1'b0, op_dst[15:9], op_dst[8] & op_bit8_msk, op_dst[7:0]};
153 // Clear the source operand (= jump offset) for conditional jumps
154 wire jmp_not_taken = (inst_jmp[`JL] & ~(status[3]^status[2])) |
155 (inst_jmp[`JGE] & (status[3]^status[2])) |
156 (inst_jmp[`JN] & ~status[2]) |
157 (inst_jmp[`JC] & ~status[0]) |
158 (inst_jmp[`JNC] & status[0]) |
159 (inst_jmp[`JEQ] & ~status[1]) |
160 (inst_jmp[`JNE] & status[1]);
161 wire [16:0] op_src_in_jmp = op_src_in & {17{~jmp_not_taken}};
163 // Adder / AND / OR / XOR
164 wire [16:0] alu_add = op_src_in_jmp + op_dst_in;
165 wire [16:0] alu_and = op_src_in & op_dst_in;
166 wire [16:0] alu_or = op_src_in | op_dst_in;
167 wire [16:0] alu_xor = op_src_in ^ op_dst_in;
171 wire alu_inc = exec_cycle & ((inst_alu[`ALU_INC_C] & status[0]) |
173 wire [16:0] alu_add_inc = alu_add + {16'h0000, alu_inc};
177 // Decimal adder (DADD)
178 wire [4:0] alu_dadd0 = bcd_add(op_src_in[3:0], op_dst_in[3:0], status[0]);
179 wire [4:0] alu_dadd1 = bcd_add(op_src_in[7:4], op_dst_in[7:4], alu_dadd0[4]);
180 wire [4:0] alu_dadd2 = bcd_add(op_src_in[11:8], op_dst_in[11:8], alu_dadd1[4]);
181 wire [4:0] alu_dadd3 = bcd_add(op_src_in[15:12], op_dst_in[15:12],alu_dadd2[4]);
182 wire [16:0] alu_dadd = {alu_dadd3, alu_dadd2[3:0], alu_dadd1[3:0], alu_dadd0[3:0]};
185 // Shifter for rotate instructions (RRC & RRA)
186 wire alu_shift_msb = inst_so[`RRC] ? status[0] :
187 inst_bw ? op_src[7] : op_src[15];
188 wire alu_shift_7 = inst_bw ? alu_shift_msb : op_src[8];
189 wire [16:0] alu_shift = {1'b0, alu_shift_msb, op_src[15:9], alu_shift_7, op_src[7:1]};
192 // Swap bytes / Extend Sign
193 wire [16:0] alu_swpb = {1'b0, op_src[7:0],op_src[15:8]};
194 wire [16:0] alu_sxt = {1'b0, {8{op_src[7]}},op_src[7:0]};
197 // Combine short paths toghether to simplify final ALU mux
198 wire alu_short_thro = ~(inst_alu[`ALU_AND] |
201 inst_alu[`ALU_SHIFT] |
205 wire [16:0] alu_short = ({16{inst_alu[`ALU_AND]}} & alu_and) |
206 ({16{inst_alu[`ALU_OR]}} & alu_or) |
207 ({16{inst_alu[`ALU_XOR]}} & alu_xor) |
208 ({16{inst_alu[`ALU_SHIFT]}} & alu_shift) |
209 ({16{inst_so[`SWPB]}} & alu_swpb) |
210 ({16{inst_so[`SXT]}} & alu_sxt) |
211 ({16{alu_short_thro}} & op_src_in);
215 wire [16:0] alu_out_nxt = (inst_so[`IRQ] | dbg_halt_st |
216 inst_alu[`ALU_ADD]) ? alu_add_inc :
217 inst_alu[`ALU_DADD] ? alu_dadd : alu_short;
219 assign alu_out = alu_out_nxt[15:0];
220 assign alu_out_add = alu_add[15:0];
223 //-----------------------------------------------------------------------------
224 // STATUS FLAG GENERATION
225 //-----------------------------------------------------------------------------
227 wire V_xor = inst_bw ? (op_src_in[7] & op_dst_in[7]) :
228 (op_src_in[15] & op_dst_in[15]);
230 wire V = inst_bw ? ((~op_src_in[7] & ~op_dst_in[7] & alu_out[7]) |
231 ( op_src_in[7] & op_dst_in[7] & ~alu_out[7])) :
232 ((~op_src_in[15] & ~op_dst_in[15] & alu_out[15]) |
233 ( op_src_in[15] & op_dst_in[15] & ~alu_out[15]));
235 wire N = inst_bw ? alu_out[7] : alu_out[15];
236 wire Z = inst_bw ? (alu_out[7:0]==0) : (alu_out==0);
237 wire C = inst_bw ? alu_out[8] : alu_out_nxt[16];
239 assign alu_stat = inst_alu[`ALU_SHIFT] ? {1'b0, N,Z,op_src_in[0]} :
240 inst_alu[`ALU_STAT_7] ? {1'b0, N,Z,~Z} :
241 inst_alu[`ALU_XOR] ? {V_xor,N,Z,~Z} : {V,N,Z,C};
243 assign alu_stat_wr = (inst_alu[`ALU_STAT_F] & exec_cycle) ? 4'b1111 : 4'b0000;
246 endmodule // omsp_alu
248 `include "openMSP430_undefines.v"