rst_i : IN STD_LOGIC;
halt_i : IN STD_LOGIC;
int_i : IN STD_LOGIC;
+ trace_i : IN STD_LOGIC;
+ trace_kick_i : IN STD_LOGIC;
+ core_clk_en_o : OUT STD_LOGIC;
-- specific fetch i/o
imem_addr_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
imem_clken_o : OUT STD_LOGIC;
SIGNAL rst_r : STD_LOGIC;
SIGNAL reset_s : STD_LOGIC;
+ SIGNAL core_clk_en_s : STD_LOGIC;
SIGNAL ID2EX_REG_r : ID2EX_Type;
SIGNAL EX2IF_REG_r : EX2IF_Type;
reset_s <= rst_i OR rst_r;
pc_ctrl_o <= NOT rst_r;
imem_addr_o <= IF2ID_REG_i.program_counter;
+ -- Tracing
+ -- Reset_s is 1 when rst_i is one and then gets deactivated
+ core_clk_en_s <= reset_s OR (NOT trace_i) OR trace_kick_i;
+ core_clk_en_o <= core_clk_en_s;
-- clock/wait control lines
clken_s <= MEM2CTRL_i.clken OR rst_i;
clken_pipe_s <= clken_s AND (NOT HAZARD_WRB_i.hazard);
INT_CTRL_o.int_busy <= int_busy_r;
regd_proc:
- PROCESS ( clk_i, rst_i, halt_i,
+ PROCESS ( clk_i, rst_i, halt_i, core_clk_en_s,
-- complete sensitivity list for synthesizer
reset_s, MEM2CTRL_i, clken_pipe_s, IF2ID_REG_i,
flush_ID2EX_s, flush_EX2MEM_s, HAZARD_WRB_i,
END PROCEDURE;
BEGIN
- IF (RISING_EDGE (clk_i) AND (MEM2CTRL_i.clken = '1')) AND halt_i = '0' THEN
+
+ IF (RISING_EDGE (clk_i) AND (MEM2CTRL_i.clken = '1')) AND halt_i = '0' AND
+ core_clk_en_s = '1' THEN
rst_r <= rst_i;
IF (reset_s = '1') THEN -- synchronous reset ...
lp_rst_IF2ID_REG; -- ... so lasts at least one clock_cycle