-- Faculty EEMCS, Department ME&CE, Circuits and Systems
-- Date: September, 2010
--
--- Modified: June, 2011: ALU_ACTION_Type extended to incorporate
+-- Modified: September, 2013: Removed FSL
+-- June, 2011: ALU_ACTION_Type extended to incorporate
-- MUL and BS instructions (Huib)
-- Adapted to work with separate fsl_M-
-- and fsl_S selectors and automatic
TYPE ALU_ACTION_Type IS (A_NOP, A_ADD, A_CMP, A_CMPU, A_OR, A_AND, A_XOR,
A_SHIFT, A_SEXT8, A_SEXT16, A_MFS, A_MTS,
- A_MUL, A_BSLL, A_BSRL, A_BSRA,
- A_FSL_GET, A_FSL_PUT);
+ A_MUL, A_BSLL, A_BSRL, A_BSRA);
TYPE ALU_IN1_Type IS (ALU_IN_REGA, ALU_IN_NOT_REGA, ALU_IN_PC, ALU_IN_ZERO);
TYPE ALU_IN2_Type IS (ALU_IN_REGB, ALU_IN_NOT_REGB, ALU_IN_IMM, ALU_IN_NOT_IMM);
TYPE ALU_CIN_Type IS (CIN_ZERO, CIN_ONE, FROM_MSR, FROM_IN1);
TYPE MSR_ACTION_Type IS (UPDATE_CARRY, KEEP_CARRY);
TYPE BRANCH_ACTION_Type IS (NO_BR, BR, BRL, BEQ, BNE, BLT, BLE, BGT, BGE);
- TYPE WRB_ACTION_Type IS (NO_WRB, WRB_EX, WRB_MEM, WRB_FSL);
+ TYPE WRB_ACTION_Type IS (NO_WRB, WRB_EX, WRB_MEM);
TYPE MEM_ACTION_Type IS (NO_MEM, WR_MEM, RD_MEM);
TYPE TRANSFER_SIZE_Type IS (WORD, HALFWORD, BYTE);
TYPE SAVE_REG_Type IS (NO_SAVE, SAVE_RA, SAVE_RB);
mem_Action : MEM_ACTION_Type; -- rd_mem implies writeback
transfer_Size : TRANSFER_SIZE_Type;
wrb_Action : WRB_ACTION_Type;
- FSL_Non_blocking : STD_LOGIC; -- ncta
- FSL_Control : STD_LOGIC;
- FSL_Test : STD_LOGIC;
- FSL_Atomic : STD_LOGIC;
END RECORD;
TYPE ID2GPRF_Type IS RECORD
TYPE MSR_Type IS RECORD
IE : STD_LOGIC; -- MSR[VHDL b1] = [MicroBlaze b30]
C : STD_LOGIC; -- MSR[VHDL b2 and b31] = [MicroBlaze b29 and b0]
- FSL : STD_LOGIC; -- MSR[VHDL b4] = [MicroBlaze b27]
END RECORD;
TYPE EX2IF_Type IS RECORD
data_rD : STD_LOGIC_VECTOR (31 DOWNTO 0);
END RECORD;
- TYPE EX2FSL_M_Type IS RECORD
- FSLx_M : STD_LOGIC_VECTOR ( 3 DOWNTO 0);
- M_Write : STD_LOGIC;
- M_Data : STD_LOGIC_VECTOR (31 DOWNTO 0);
- M_Control : STD_LOGIC;
- END RECORD;
-
- TYPE FSL_M2EX_Type IS RECORD
- M_Full : STD_LOGIC;
- END RECORD;
-
- TYPE EX2FSL_S_Type IS RECORD
- FSLx_S : STD_LOGIC_VECTOR ( 3 DOWNTO 0);
- S_Read : STD_LOGIC;
- END RECORD;
-
- TYPE FSL_S2EX_Type IS RECORD
- S_Control : STD_LOGIC;
- S_Exists : STD_LOGIC;
- END RECORD;
-
- TYPE FSL_S2MEM_Type IS RECORD
- S_Data : STD_LOGIC_VECTOR (31 DOWNTO 0);
- END RECORD;
-
TYPE MEM_REG_Type IS RECORD
wrb_Action : WRB_ACTION_Type;
exeq_result : STD_LOGIC_VECTOR (31 DOWNTO 0);
-- NOTE: Use the named association format xxxx := ( 0 => X"A0010000" );
-- in case the array has to contain only one element !!
- TYPE CORE2FSL_M_Type IS RECORD
- -- connect M_Clk directly to highest level clock
- M_Write : STD_LOGIC;
- M_Data : STD_LOGIC_VECTOR (31 DOWNTO 0);
- M_Control : STD_LOGIC;
- END RECORD;
-
- TYPE FSL_M2CORE_Type IS RECORD
- M_Full : STD_LOGIC;
- END RECORD;
-
- TYPE CORE2FSL_S_Type IS RECORD
- -- connect S_Clk directly to highest level clock
- S_Read : STD_LOGIC;
- END RECORD;
-
- TYPE FSL_S2CORE_Type IS RECORD
- S_Exists : STD_LOGIC;
- S_Data : STD_LOGIC_VECTOR (31 DOWNTO 0);
- S_Control : STD_LOGIC;
- END RECORD;
-
- TYPE CORE2FSL_M_ARRAY_Type IS ARRAY(NATURAL RANGE <>) OF CORE2FSL_M_Type;
- TYPE FSL_M2CORE_ARRAY_Type IS ARRAY(NATURAL RANGE <>) OF FSL_M2CORE_Type;
- TYPE CORE2FSL_S_ARRAY_Type IS ARRAY(NATURAL RANGE <>) OF CORE2FSL_S_Type;
- TYPE FSL_S2CORE_ARRAY_Type IS ARRAY(NATURAL RANGE <>) OF FSL_S2CORE_Type;
-
-
----------------------------------------------------------------------------------------------
-- COMPONENTS
----------------------------------------------------------------------------------------------
INT_CTRL_i : IN INT_CTRL_Type;
ID2CTRL_o : OUT ID2CTRL_Type;
--
- noLiteOpc_s : OUT STD_LOGIC
+ noLiteOpc_o : OUT STD_LOGIC
);
END COMPONENT;
MSR_i : IN MSR_Type;
MSR_o : OUT MSR_Type;
--
- EX2MEM_o : OUT EX2MEM_Type;
- --
- exq_branch_i : IN STD_LOGIC;
- --
- FSL_M2EX_i : IN FSL_M2EX_Type;
- EX2FSL_M_o : OUT EX2FSL_M_Type;
- --
- FSL_S2EX_i : IN FSL_S2EX_Type;
- EX2FSL_S_o : OUT EX2FSL_S_Type;
- --
- FSL_nStall_o : OUT STD_LOGIC
+ EX2MEM_o : OUT EX2MEM_Type
);
END COMPONENT;
DMEMB_i : IN DMEMB2CORE_Type;
DMEMB_o : OUT CORE2DMEMB_Type;
--
- FSL_S2MEM_i : IN FSL_S2MEM_Type;
- --
MEM_REG_i : IN MEM_REG_Type;
MEM_REG_o : OUT MEM_REG_Type;
--
rst_i : IN STD_LOGIC;
halt_i : IN STD_LOGIC;
int_i : IN STD_LOGIC;
+ trace_i : IN STD_LOGIC;
+ trace_kick_i : IN STD_LOGIC;
+ core_clk_en_o : OUT STD_LOGIC;
-- specific fetch i/o
imem_addr_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
imem_clken_o : OUT STD_LOGIC;
-- decode control i/o
ID2CTRL_i : IN ID2CTRL_Type;
INT_CTRL_o : OUT INT_CTRL_Type;
- -- FSL to mem data delay register(s)
- FSL_S2MEM_REG_i : IN FSL_S2MEM_Type;
- FSL_S2MEM_REG_o : OUT FSL_S2MEM_Type;
-- exeq control i/o
EX_WRB_i : IN WRB_Type;
EX_WRB_o : OUT WRB_Type;
MSR_o : OUT MSR_Type;
-- miscellaneous
MEM2CTRL_i : IN MEM2CTRL_Type;
- FSL_nStall_i : IN STD_LOGIC;
done_o : OUT STD_LOGIC
);
END COMPONENT;
- COMPONENT fsl_M_selector IS
- GENERIC (
- N_FSL_M_g : POSITIVE RANGE 1 TO 16 := 1 -- 1 upto 16
- );
- PORT (
- EX2FSL_M_i : IN EX2FSL_M_Type;
- FSL_M2EX_o : OUT FSL_M2EX_Type;
- --
- FSL_M_ARRAY_i : IN FSL_M2CORE_ARRAY_Type (0 TO N_FSL_M_g -1);
- FSL_M_ARRAY_o : OUT CORE2FSL_M_ARRAY_Type (0 TO N_FSL_M_g -1)
- );
- END COMPONENT;
-
- COMPONENT fsl_S_selector IS
- GENERIC (
- N_FSL_S_g : POSITIVE RANGE 1 TO 16 := 1 -- 1 upto 16
- );
- PORT (
- EX2FSL_S_i : IN EX2FSL_S_Type;
- FSL_S2EX_o : OUT FSL_S2EX_Type;
- FSL_S2MEM_o : OUT FSL_S2MEM_Type;
- --
- FSL_S_ARRAY_i : IN FSL_S2CORE_ARRAY_Type (0 TO N_FSL_S_g -1);
- FSL_S_ARRAY_o : OUT CORE2FSL_S_ARRAY_Type (0 TO N_FSL_S_g -1)
- );
- END COMPONENT;
-
----------------------------------------------------------------------------------------------
-- FUNCTION, PROCEDURE DECLARATIONS
----------------------------------------------------------------------------------------------
projects / fpga / lx-cpu1 / tumbl.git / blobdiff