1 ---------------------------------------------------------------------------------
4 -- Filename: core_ctrl.vhd
5 -- Description: the control unit for the TUD MB-Lite implementation
7 -- Author: Huib Lincklaen Arriens
8 -- Delft University of Technology
9 -- Faculty EEMCS, Department ME&CE, Circuits and Systems
10 -- Date: December, 2010
11 -- Modified: September, 2012: interrupt handling corrected to let
12 -- a pending branch be taken first
13 -- (with thanks to Matthis Meier, TU Dortmund,
14 -- for detecting this errror).
17 --------------------------------------------------------------------------------
21 USE IEEE.std_logic_1164.all;
25 --------------------------------------------------------------------------------
27 --------------------------------------------------------------------------------
31 halt_i : IN STD_LOGIC;
33 trace_i : IN STD_LOGIC;
34 trace_kick_i : IN STD_LOGIC;
35 core_clk_en_o : OUT STD_LOGIC;
37 imem_addr_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
38 imem_clken_o : OUT STD_LOGIC;
39 pc_ctrl_o : OUT STD_LOGIC;
40 -- fetch to decode pipeline registers
41 IF2ID_REG_i : IN IF2ID_Type;
42 IF2ID_REG_o : OUT IF2ID_Type;
43 -- decode to exeq pipeline registers
44 ID2EX_REG_i : IN ID2EX_Type;
45 ID2EX_REG_o : OUT ID2EX_Type;
47 gprf_clken_o : OUT STD_LOGIC;
48 -- exeq to fetch feedback registers
49 EX2IF_REG_i : IN EX2IF_Type;
50 EX2IF_REG_o : OUT EX2IF_Type;
51 -- exeq to mem pipeline registers
52 EX2MEM_REG_i : IN EX2MEM_Type;
53 EX2MEM_REG_o : OUT EX2MEM_Type;
54 -- mem pipeline register
55 MEM_REG_i : IN MEM_REG_Type;
56 MEM_REG_o : OUT MEM_REG_Type;
58 ID2CTRL_i : IN ID2CTRL_Type;
59 INT_CTRL_o : OUT INT_CTRL_Type;
61 EX_WRB_i : IN WRB_Type;
62 EX_WRB_o : OUT WRB_Type;
64 HAZARD_WRB_i : IN HAZARD_WRB_Type;
65 HAZARD_WRB_o : OUT HAZARD_WRB_Type;
66 -- for handling the 'IMM' instruction
67 IMM_LOCK_i : IN IMM_LOCK_Type;
68 IMM_LOCK_o : OUT IMM_LOCK_Type;
69 -- for handling the Machine Status Register
73 MEM2CTRL_i : IN MEM2CTRL_Type;
74 done_o : OUT STD_LOGIC
78 --------------------------------------------------------------------------------
79 ARCHITECTURE rtl OF core_ctrl IS
80 --------------------------------------------------------------------------------
82 SIGNAL rst_r : STD_LOGIC;
83 SIGNAL reset_s : STD_LOGIC;
84 SIGNAL core_clk_en_s : STD_LOGIC;
86 SIGNAL ID2EX_REG_r : ID2EX_Type;
87 SIGNAL EX2IF_REG_r : EX2IF_Type;
88 SIGNAL delayBit_r : STD_LOGIC;
89 SIGNAL delayBit_2r : STD_LOGIC;
90 SIGNAL IMM_LOCK_r : IMM_LOCK_Type;
91 SIGNAL HAZARD_WRB_r : HAZARD_WRB_Type;
93 SIGNAL clken_s : STD_LOGIC;
94 SIGNAL clken_pipe_s : STD_LOGIC;
95 SIGNAL flush_ID2EX_s : STD_LOGIC;
96 SIGNAL flush_ID2EX_r : STD_LOGIC;
97 SIGNAL flush_EX2MEM_s : STD_LOGIC;
99 SIGNAL setup_int_r : STD_LOGIC;
100 SIGNAL int_busy_r : STD_LOGIC;
105 -- static connections
106 reset_s <= rst_i OR rst_r;
107 pc_ctrl_o <= NOT rst_r;
108 imem_addr_o <= IF2ID_REG_i.program_counter;
110 -- Reset_s is 1 when rst_i is one and then gets deactivated
111 core_clk_en_s <= reset_s OR (NOT trace_i) OR trace_kick_i;
112 core_clk_en_o <= core_clk_en_s;
113 -- clock/wait control lines
114 clken_s <= MEM2CTRL_i.clken OR rst_i;
115 clken_pipe_s <= clken_s AND (NOT HAZARD_WRB_i.hazard);
116 imem_clken_o <= clken_pipe_s;
117 gprf_clken_o <= clken_s;
118 -- signals for clearing the ID2EX and EX2MEM registers during branches
119 flush_ID2EX_s <= EX2IF_REG_r.take_branch;
120 flush_EX2MEM_s <= (flush_ID2EX_s AND (NOT delayBit_2r)) OR HAZARD_WRB_i.hazard;
121 -- outputs that need to be readable too, so needing shadowing signals
122 ID2EX_REG_o <= ID2EX_REG_r;
123 EX2IF_REG_o <= EX2IF_REG_r;
124 IMM_LOCK_o <= IMM_LOCK_r;
125 HAZARD_WRB_o <= HAZARD_WRB_r;
127 INT_CTRL_o.setup_int <= setup_int_r;
128 INT_CTRL_o.rti_target <= ID2EX_REG_r.program_counter;
129 INT_CTRL_o.int_busy <= int_busy_r;
132 PROCESS ( clk_i, rst_i, halt_i, core_clk_en_s,
133 -- complete sensitivity list for synthesizer
134 reset_s, MEM2CTRL_i, clken_pipe_s, IF2ID_REG_i,
135 flush_ID2EX_s, flush_EX2MEM_s, HAZARD_WRB_i,
136 MEM_REG_i, ID2CTRL_i, int_i, MSR_i,
137 int_busy_r, delayBit_r, IMM_LOCK_i, ID2EX_REG_i, ID2EX_REG_r,
138 EX2IF_REG_i, EX_WRB_i, EX2MEM_REG_i )
140 -- some local procedures
141 PROCEDURE lp_rst_IF2ID_REG IS
143 IF2ID_REG_o.program_counter <= (OTHERS => '0');
146 PROCEDURE lp_rst_ID2EX_REG IS
148 -- reset and handle ID2EX_REG_r.program_counter separately,
149 -- since it will be needed during interrupt setup
150 ID2EX_REG_r.rdix_rA <= (OTHERS => '0');
151 ID2EX_REG_r.rdix_rB <= (OTHERS => '0');
152 ID2EX_REG_r.curr_rD <= (OTHERS => '0');
153 ID2EX_REG_r.alu_Action <= A_NOP;
154 ID2EX_REG_r.alu_Op1 <= ALU_IN_ZERO;
155 ID2EX_REG_r.alu_Op2 <= ALU_IN_IMM;
156 ID2EX_REG_r.alu_Cin <= CIN_ZERO;
157 ID2EX_REG_r.IMM16 <= (OTHERS => '0');
158 ID2EX_REG_r.IMM_Lock <= '0';
159 ID2EX_REG_r.msr_Action <= KEEP_CARRY;
160 ID2EX_REG_r.branch_Action <= NO_BR;
161 ID2EX_REG_r.mem_Action <= NO_MEM;
162 ID2EX_REG_r.transfer_Size <= WORD;
163 ID2EX_REG_r.wrb_Action <= NO_WRB;
166 PROCEDURE lp_rst_EX2IF_REG IS
168 EX2IF_REG_r.take_branch <= '0';
169 EX2IF_REG_r.branch_target <= (OTHERS => '0');
172 PROCEDURE lp_rst_EX2MEM_REG IS
174 EX2MEM_REG_o.mem_Action <= NO_MEM;
175 EX2MEM_REG_o.wrb_Action <= NO_WRB;
176 EX2MEM_REG_o.exeq_result <= (OTHERS => '0');
177 EX2MEM_REG_o.data_rD <= (OTHERS => '0');
178 EX2MEM_REG_o.byte_Enable <= (OTHERS => '0');
179 EX2MEM_REG_o.wrix_rD <= (OTHERS => '0');
182 PROCEDURE lp_rst_IMM_LOCK IS
184 IMM_LOCK_r.locked <= '0';
185 IMM_LOCK_r.IMM_hi16 <= (OTHERS => '0');
188 PROCEDURE lp_rst_MSR IS
194 PROCEDURE lp_rst_EX_WRB IS
196 EX_WRB_o.wrb_Action <= NO_WRB;
197 EX_WRB_o.wrix_rD <= (OTHERS => '0');
198 EX_WRB_o.data_rD <= (OTHERS => '0');
201 PROCEDURE lp_rst_HAZARD_WRB IS
203 HAZARD_WRB_r.hazard <= '0';
204 HAZARD_WRB_r.save_rX <= NO_SAVE;
205 HAZARD_WRB_r.data_rX <= (OTHERS => '0');
206 HAZARD_WRB_r.data_rD <= (OTHERS => '0');
209 PROCEDURE lp_rst_MEM_REG IS
211 MEM_REG_o.wrb_Action <= NO_WRB;
212 MEM_REG_o.exeq_result <= (OTHERS => '0');
213 MEM_REG_o.byte_Enable <= (OTHERS => '0');
214 MEM_REG_o.wrix_rD <= (OTHERS => '0');
219 IF (RISING_EDGE (clk_i) AND (MEM2CTRL_i.clken = '1')) AND halt_i = '0' AND
220 core_clk_en_s = '1' THEN
222 IF (reset_s = '1') THEN -- synchronous reset ...
223 lp_rst_IF2ID_REG; -- ... so lasts at least one clock_cycle
228 flush_ID2EX_r <= '0';
232 ID2EX_REG_r.program_counter <= (OTHERS => '0');
234 IF (clken_pipe_s = '1') THEN
235 IF2ID_REG_o <= IF2ID_REG_i;
237 flush_ID2EX_r <= flush_ID2EX_s;
238 HAZARD_WRB_r <= HAZARD_WRB_i;
239 MEM_REG_o <= MEM_REG_i;
240 int_busy_r <= ID2CTRL_i.int_busy;
242 -- decode-to-exeq unit registers
243 IF ((reset_s = '1') OR (flush_ID2EX_s = '1')) THEN
246 -- check for the need and possibility to handle active interrupt requests
247 ELSIF (((int_i = '1') OR (MEM2CTRL_i.int = '1')) AND (MSR_i.IE = '1') AND
248 (ID2CTRL_i.int_busy = '0') AND (int_busy_r = '0') AND
249 -- pending branch should be taken before interrupt can be executed
250 -- dectected by Matthis Meier, TU Dortmund (Sept 2012)
251 (EX2IF_REG_i.take_branch = '0') AND
252 (delayBit_r = '0') AND
253 (IMM_LOCK_i.locked = '0') AND
254 (HAZARD_WRB_i.hazard = '0')) THEN
256 ID2EX_REG_r.program_counter <= ID2EX_REG_i.program_counter;
258 ELSIF (clken_pipe_s = '1') THEN
260 ID2EX_REG_r <= ID2EX_REG_i;
261 delayBit_r <= ID2CTRL_i.delayBit;
263 -- exeq-to-mem unit registers
264 IF ((reset_s = '1') OR (flush_EX2MEM_s = '1')) THEN
271 IF (clken_pipe_s = '1') THEN
272 EX2IF_REG_r <= EX2IF_REG_i;
273 delayBit_2r <= delayBit_r;
274 EX_WRB_o <= EX_WRB_i;
276 IF (clken_s = '1') THEN
277 -- next test to prevent a flush from disrupting
278 -- the write-back pipeline
279 IF (flush_ID2EX_r = '0') THEN
280 EX2MEM_REG_o <= EX2MEM_REG_i;
282 IMM_LOCK_r <= IMM_LOCK_i;
286 -- check on End-Of-Program viz. "bri 0x00"
287 -- use delayBit to distinguish between "bri" and "rtsd/rtid"
288 IF ((ID2EX_REG_r.branch_Action = BR) AND
289 (ID2EX_REG_r.alu_Op2 = ALU_IN_IMM) AND
290 (ID2EX_REG_r.IMM16 = C_16_ZEROS) AND
291 (delayBit_r = '0') AND (flush_EX2MEM_s = '0')) THEN
294 END IF; -- rising edge clk_i ...
295 END PROCESS regd_proc;
297 END ARCHITECTURE rtl;