1 ---------------------------------------------------------------------------------
4 -- Filename: mbl_Pkg.vhd
5 -- Description: Package for the TUD MB-Lite implementation
7 -- Author: Huib Lincklaen Arriens
8 -- Delft University of Technology
9 -- Faculty EEMCS, Department ME&CE, Circuits and Systems
10 -- Date: September, 2010
12 -- Modified: June, 2011: ALU_ACTION_Type extended to incorporate
13 -- MUL and BS instructions (Huib)
14 -- Adapted to work with separate fsl_M-
15 -- and fsl_S selectors and automatic
16 -- tumbl<_jtag><_fsl>.vhd generation (Huib)
17 -- July, 2011: function ef_nbits added (Huib)
20 --------------------------------------------------------------------------------
23 USE IEEE.std_logic_1164.all;
24 USE IEEE.std_logic_unsigned.all;
25 USE IEEE.numeric_std.all;
28 --------------------------------------------------------------------------------
30 --------------------------------------------------------------------------------
32 CONSTANT C_8_ZEROS : STD_LOGIC_VECTOR ( 7 DOWNTO 0) := X"00";
33 CONSTANT C_16_ZEROS : STD_LOGIC_VECTOR (15 DOWNTO 0) := X"0000";
34 CONSTANT C_24_ZEROS : STD_LOGIC_VECTOR (23 DOWNTO 0) := X"000000";
35 CONSTANT C_32_ZEROS : STD_LOGIC_VECTOR (31 DOWNTO 0) := X"00000000";
37 CONSTANT C_16_ONES : STD_LOGIC_VECTOR (15 DOWNTO 0) := X"FFFF";
38 CONSTANT C_24_ONES : STD_LOGIC_VECTOR (23 DOWNTO 0) := X"FFFFFF";
41 ----------------------------------------------------------------------------------------------
43 ----------------------------------------------------------------------------------------------
45 TYPE ALU_ACTION_Type IS (A_NOP, A_ADD, A_CMP, A_CMPU, A_OR, A_AND, A_XOR,
46 A_SHIFT, A_SEXT8, A_SEXT16, A_MFS, A_MTS,
47 A_MUL, A_BSLL, A_BSRL, A_BSRA,
48 A_FSL_GET, A_FSL_PUT);
49 TYPE ALU_IN1_Type IS (ALU_IN_REGA, ALU_IN_NOT_REGA, ALU_IN_PC, ALU_IN_ZERO);
50 TYPE ALU_IN2_Type IS (ALU_IN_REGB, ALU_IN_NOT_REGB, ALU_IN_IMM, ALU_IN_NOT_IMM);
51 TYPE ALU_CIN_Type IS (CIN_ZERO, CIN_ONE, FROM_MSR, FROM_IN1);
52 TYPE MSR_ACTION_Type IS (UPDATE_CARRY, KEEP_CARRY);
53 TYPE BRANCH_ACTION_Type IS (NO_BR, BR, BRL, BEQ, BNE, BLT, BLE, BGT, BGE);
54 TYPE WRB_ACTION_Type IS (NO_WRB, WRB_EX, WRB_MEM, WRB_FSL);
55 TYPE MEM_ACTION_Type IS (NO_MEM, WR_MEM, RD_MEM);
56 TYPE TRANSFER_SIZE_Type IS (WORD, HALFWORD, BYTE);
57 TYPE SAVE_REG_Type IS (NO_SAVE, SAVE_RA, SAVE_RB);
59 TYPE IF2ID_Type IS RECORD
60 program_counter : STD_LOGIC_VECTOR (31 DOWNTO 0);
63 TYPE ID2EX_Type IS RECORD
64 program_counter : STD_LOGIC_VECTOR (31 DOWNTO 0);
65 rdix_rA : STD_LOGIC_VECTOR ( 4 DOWNTO 0);
66 rdix_rB : STD_LOGIC_VECTOR ( 4 DOWNTO 0);
67 curr_rD : STD_LOGIC_VECTOR ( 4 DOWNTO 0);
68 alu_Action : ALU_ACTION_Type;
69 alu_Op1 : ALU_IN1_Type;
70 alu_Op2 : ALU_IN2_Type;
71 alu_Cin : ALU_CIN_Type;
72 IMM16 : STD_LOGIC_VECTOR (15 DOWNTO 0);
74 msr_Action : MSR_ACTION_Type;
75 branch_Action : BRANCH_ACTION_Type;
76 mem_Action : MEM_ACTION_Type; -- rd_mem implies writeback
77 transfer_Size : TRANSFER_SIZE_Type;
78 wrb_Action : WRB_ACTION_Type;
79 FSL_Non_blocking : STD_LOGIC; -- ncta
80 FSL_Control : STD_LOGIC;
82 FSL_Atomic : STD_LOGIC;
85 TYPE ID2GPRF_Type IS RECORD
86 rdix_rA : STD_LOGIC_VECTOR ( 4 DOWNTO 0);
87 rdix_rB : STD_LOGIC_VECTOR ( 4 DOWNTO 0);
88 rdix_rD : STD_LOGIC_VECTOR ( 4 DOWNTO 0);
91 TYPE INT_CTRL_Type IS RECORD
92 setup_int : STD_LOGIC;
93 rti_target : STD_LOGIC_VECTOR (31 DOWNTO 0);
97 TYPE ID2CTRL_Type IS RECORD
102 TYPE GPRF2EX_Type IS RECORD
103 data_rA : STD_LOGIC_VECTOR (31 DOWNTO 0);
104 data_rB : STD_LOGIC_VECTOR (31 DOWNTO 0);
105 data_rD : STD_LOGIC_VECTOR (31 DOWNTO 0);
108 TYPE IMM_LOCK_Type IS RECORD
110 IMM_hi16 : STD_LOGIC_VECTOR (15 DOWNTO 0);
113 TYPE MSR_Type IS RECORD
114 IE : STD_LOGIC; -- MSR[VHDL b1] = [MicroBlaze b30]
115 C : STD_LOGIC; -- MSR[VHDL b2 and b31] = [MicroBlaze b29 and b0]
116 FSL : STD_LOGIC; -- MSR[VHDL b4] = [MicroBlaze b27]
119 TYPE EX2IF_Type IS RECORD
120 take_branch : STD_LOGIC;
121 branch_target : STD_LOGIC_VECTOR (31 DOWNTO 0);
124 TYPE EX2MEM_Type IS RECORD
125 mem_Action : MEM_ACTION_Type; -- RD_MEM implies writeback
126 wrb_Action : WRB_ACTION_Type;
127 exeq_result : STD_LOGIC_VECTOR (31 DOWNTO 0);
128 data_rD : STD_LOGIC_VECTOR (31 DOWNTO 0);
129 byte_Enable : STD_LOGIC_VECTOR ( 3 DOWNTO 0);
130 wrix_rD : STD_LOGIC_VECTOR ( 4 DOWNTO 0);
133 TYPE WRB_Type IS RECORD
134 wrb_Action : WRB_ACTION_Type;
135 wrix_rD : STD_LOGIC_VECTOR ( 4 DOWNTO 0);
136 data_rD : STD_LOGIC_VECTOR (31 DOWNTO 0);
139 TYPE HAZARD_WRB_Type IS RECORD
141 save_rX : SAVE_REG_Type;
142 data_rX : STD_LOGIC_VECTOR (31 DOWNTO 0);
143 data_rD : STD_LOGIC_VECTOR (31 DOWNTO 0);
146 TYPE EX2FSL_M_Type IS RECORD
147 FSLx_M : STD_LOGIC_VECTOR ( 3 DOWNTO 0);
149 M_Data : STD_LOGIC_VECTOR (31 DOWNTO 0);
150 M_Control : STD_LOGIC;
153 TYPE FSL_M2EX_Type IS RECORD
157 TYPE EX2FSL_S_Type IS RECORD
158 FSLx_S : STD_LOGIC_VECTOR ( 3 DOWNTO 0);
162 TYPE FSL_S2EX_Type IS RECORD
163 S_Control : STD_LOGIC;
164 S_Exists : STD_LOGIC;
167 TYPE FSL_S2MEM_Type IS RECORD
168 S_Data : STD_LOGIC_VECTOR (31 DOWNTO 0);
171 TYPE MEM_REG_Type IS RECORD
172 wrb_Action : WRB_ACTION_Type;
173 exeq_result : STD_LOGIC_VECTOR (31 DOWNTO 0);
174 byte_Enable : STD_LOGIC_VECTOR ( 3 DOWNTO 0);
175 wrix_rD : STD_LOGIC_VECTOR ( 4 DOWNTO 0);
178 TYPE MEM2CTRL_Type IS RECORD
183 TYPE CORE2DMEMB_Type IS RECORD
185 addr : STD_LOGIC_VECTOR (31 DOWNTO 0);
186 bSel : STD_LOGIC_VECTOR ( 3 DOWNTO 0);
188 data : STD_LOGIC_VECTOR (31 DOWNTO 0);
191 TYPE DMEMB2CORE_Type IS RECORD
193 data : STD_LOGIC_VECTOR (31 DOWNTO 0);
197 TYPE MEMORY_MAP_Type IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR (31 DOWNTO 0);
198 -- NOTE: Use the named association format xxxx := ( 0 => X"A0010000" );
199 -- in case the array has to contain only one element !!
201 TYPE CORE2FSL_M_Type IS RECORD
202 -- connect M_Clk directly to highest level clock
204 M_Data : STD_LOGIC_VECTOR (31 DOWNTO 0);
205 M_Control : STD_LOGIC;
208 TYPE FSL_M2CORE_Type IS RECORD
212 TYPE CORE2FSL_S_Type IS RECORD
213 -- connect S_Clk directly to highest level clock
217 TYPE FSL_S2CORE_Type IS RECORD
218 S_Exists : STD_LOGIC;
219 S_Data : STD_LOGIC_VECTOR (31 DOWNTO 0);
220 S_Control : STD_LOGIC;
223 TYPE CORE2FSL_M_ARRAY_Type IS ARRAY(NATURAL RANGE <>) OF CORE2FSL_M_Type;
224 TYPE FSL_M2CORE_ARRAY_Type IS ARRAY(NATURAL RANGE <>) OF FSL_M2CORE_Type;
225 TYPE CORE2FSL_S_ARRAY_Type IS ARRAY(NATURAL RANGE <>) OF CORE2FSL_S_Type;
226 TYPE FSL_S2CORE_ARRAY_Type IS ARRAY(NATURAL RANGE <>) OF FSL_S2CORE_Type;
229 ----------------------------------------------------------------------------------------------
231 ----------------------------------------------------------------------------------------------
235 prog_cntr_i : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
236 inc_pc_i : IN STD_LOGIC;
237 EX2IF_i : IN EX2IF_Type;
238 IF2ID_o : OUT IF2ID_Type
244 USE_HW_MUL_g : BOOLEAN := FALSE;
245 USE_BARREL_g : BOOLEAN := FALSE
248 IF2ID_i : IN IF2ID_Type;
249 imem_data_i : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
251 ID2GPRF_o : OUT ID2GPRF_Type;
252 ID2EX_o : OUT ID2EX_Type;
254 INT_CTRL_i : IN INT_CTRL_Type;
255 ID2CTRL_o : OUT ID2CTRL_Type;
257 noLiteOpc_s : OUT STD_LOGIC
263 DW_g : POSITIVE := 32;
264 LW_g : POSITIVE := 15
267 in1 : IN STD_LOGIC_VECTOR (DW_g-1 DOWNTO 0);
268 in2 : IN STD_LOGIC_VECTOR (DW_g-1 DOWNTO 0);
270 sum : OUT STD_LOGIC_VECTOR (DW_g-1 DOWNTO 0);
277 USE_HW_MUL_g : BOOLEAN := FALSE;
278 USE_BARREL_g : BOOLEAN := FALSE
281 ID2EX_i : IN ID2EX_Type;
282 GPRF2EX_i : IN GPRF2EX_Type;
283 EX2IF_o : OUT EX2IF_Type;
285 EX_WRB_i : IN WRB_Type;
286 EX_WRB_o : OUT WRB_Type;
287 MEM_WRB_i : IN WRB_Type;
289 HAZARD_WRB_i : IN HAZARD_WRB_Type;
290 HAZARD_WRB_o : OUT HAZARD_WRB_Type;
292 IMM_LOCK_i : IN IMM_LOCK_Type;
293 IMM_LOCK_o : OUT IMM_LOCK_Type;
296 MSR_o : OUT MSR_Type;
298 EX2MEM_o : OUT EX2MEM_Type;
300 exq_branch_i : IN STD_LOGIC;
302 FSL_M2EX_i : IN FSL_M2EX_Type;
303 EX2FSL_M_o : OUT EX2FSL_M_Type;
305 FSL_S2EX_i : IN FSL_S2EX_Type;
306 EX2FSL_S_o : OUT EX2FSL_S_Type;
308 FSL_nStall_o : OUT STD_LOGIC
314 EX2MEM_i : IN EX2MEM_Type;
316 DMEMB_i : IN DMEMB2CORE_Type;
317 DMEMB_o : OUT CORE2DMEMB_Type;
319 FSL_S2MEM_i : IN FSL_S2MEM_Type;
321 MEM_REG_i : IN MEM_REG_Type;
322 MEM_REG_o : OUT MEM_REG_Type;
324 MEM_WRB_o : OUT WRB_Type;
325 MEM2CTRL_o : OUT MEM2CTRL_Type
329 COMPONENT core_ctrl IS
331 clk_i : IN STD_LOGIC;
332 rst_i : IN STD_LOGIC;
333 halt_i : IN STD_LOGIC;
334 int_i : IN STD_LOGIC;
335 -- specific fetch i/o
336 imem_addr_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
337 imem_clken_o : OUT STD_LOGIC;
338 pc_ctrl_o : OUT STD_LOGIC;
339 -- fetch to decode pipeline registers
340 IF2ID_REG_i : IN IF2ID_Type;
341 IF2ID_REG_o : OUT IF2ID_Type;
342 -- decode to exeq pipeline registers
343 ID2EX_REG_i : IN ID2EX_Type;
344 ID2EX_REG_o : OUT ID2EX_Type;
346 gprf_clken_o : OUT STD_LOGIC;
347 -- exeq to fetch feedback registers
348 EX2IF_REG_i : IN EX2IF_Type;
349 EX2IF_REG_o : OUT EX2IF_Type;
350 -- exeq to mem pipeline registers
351 EX2MEM_REG_i : IN EX2MEM_Type;
352 EX2MEM_REG_o : OUT EX2MEM_Type;
353 -- mem pipeline register
354 MEM_REG_i : IN MEM_REG_Type;
355 MEM_REG_o : OUT MEM_REG_Type;
356 -- decode control i/o
357 ID2CTRL_i : IN ID2CTRL_Type;
358 INT_CTRL_o : OUT INT_CTRL_Type;
359 -- FSL to mem data delay register(s)
360 FSL_S2MEM_REG_i : IN FSL_S2MEM_Type;
361 FSL_S2MEM_REG_o : OUT FSL_S2MEM_Type;
363 EX_WRB_i : IN WRB_Type;
364 EX_WRB_o : OUT WRB_Type;
366 HAZARD_WRB_i : IN HAZARD_WRB_Type;
367 HAZARD_WRB_o : OUT HAZARD_WRB_Type;
368 -- for handling the 'IMM' instruction
369 IMM_LOCK_i : IN IMM_LOCK_Type;
370 IMM_LOCK_o : OUT IMM_LOCK_Type;
371 -- for handling the Machine Status Register
373 MSR_o : OUT MSR_Type;
375 MEM2CTRL_i : IN MEM2CTRL_Type;
376 FSL_nStall_i : IN STD_LOGIC;
377 done_o : OUT STD_LOGIC
381 COMPONENT fsl_M_selector IS
383 N_FSL_M_g : POSITIVE RANGE 1 TO 16 := 1 -- 1 upto 16
386 EX2FSL_M_i : IN EX2FSL_M_Type;
387 FSL_M2EX_o : OUT FSL_M2EX_Type;
389 FSL_M_ARRAY_i : IN FSL_M2CORE_ARRAY_Type (0 TO N_FSL_M_g -1);
390 FSL_M_ARRAY_o : OUT CORE2FSL_M_ARRAY_Type (0 TO N_FSL_M_g -1)
394 COMPONENT fsl_S_selector IS
396 N_FSL_S_g : POSITIVE RANGE 1 TO 16 := 1 -- 1 upto 16
399 EX2FSL_S_i : IN EX2FSL_S_Type;
400 FSL_S2EX_o : OUT FSL_S2EX_Type;
401 FSL_S2MEM_o : OUT FSL_S2MEM_Type;
403 FSL_S_ARRAY_i : IN FSL_S2CORE_ARRAY_Type (0 TO N_FSL_S_g -1);
404 FSL_S_ARRAY_o : OUT CORE2FSL_S_ARRAY_Type (0 TO N_FSL_S_g -1)
408 ----------------------------------------------------------------------------------------------
409 -- FUNCTION, PROCEDURE DECLARATIONS
410 ----------------------------------------------------------------------------------------------
412 PROCEDURE ep_add32 ( a, b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
414 VARIABLE s : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
415 VARIABLE co : OUT STD_LOGIC );
417 PROCEDURE ep_add32nc ( a, b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
419 VARIABLE s : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
421 -- PROCEDURE ep_add32 ( a, b : IN STD_LOGIC_VECTOR; ci : IN STD_LOGIC;
422 -- VARIABLE s : OUT STD_LOGIC_VECTOR;
423 -- VARIABLE co : OUT STD_LOGIC );
425 FUNCTION ef_nbits ( value : NATURAL ) RETURN POSITIVE;
430 ----------------------------------------------------------
431 PACKAGE BODY mbl_Pkg IS
432 ----------------------------------------------------------
434 PROCEDURE ep_add32 ( a, b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
436 VARIABLE s : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
437 VARIABLE co : OUT STD_LOGIC ) IS
439 CONSTANT NBITS_LO_c : POSITIVE := 17;
440 CONSTANT NBITS_HI_c : POSITIVE := 32 -NBITS_LO_c;
441 VARIABLE tmp_lo_v : STD_LOGIC_VECTOR (NBITS_LO_c +1 DOWNTO 0);
442 VARIABLE tmp_hi0_v : STD_LOGIC_VECTOR (NBITS_HI_c +1 DOWNTO 0);
443 VARIABLE tmp_hi1_v : STD_LOGIC_VECTOR (NBITS_HI_c +1 DOWNTO 0);
445 tmp_lo_v := STD_LOGIC_VECTOR( UNSIGNED( '0' & a(NBITS_LO_c -1 DOWNTO 0) & '1' ) +
446 UNSIGNED( '0' & b(NBITS_LO_c -1 DOWNTO 0) & ci ));
447 tmp_hi0_v := STD_LOGIC_VECTOR( UNSIGNED( '0' & a(31 DOWNTO (32 - NBITS_HI_c)) & '1') +
448 UNSIGNED( '0' & b(31 DOWNTO (32 - NBITS_HI_c)) & '0'));
449 tmp_hi1_v := STD_LOGIC_VECTOR( UNSIGNED( '0' & a(31 DOWNTO (32 - NBITS_HI_c)) & '1') +
450 UNSIGNED( '0' & b(31 DOWNTO (32 - NBITS_HI_c)) & '1'));
451 IF (tmp_lo_v(NBITS_LO_c +1) = '0') THEN
452 s := tmp_hi0_v(NBITS_HI_c DOWNTO 1) & tmp_lo_v(NBITS_LO_c DOWNTO 1);
453 co := tmp_hi0_v(NBITS_HI_c +1);
455 s := tmp_hi1_v(NBITS_HI_c DOWNTO 1) & tmp_lo_v(NBITS_LO_c DOWNTO 1);
456 co := tmp_hi1_v(NBITS_HI_c +1);
460 PROCEDURE ep_add32nc ( a, b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
462 VARIABLE s : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ) IS
464 CONSTANT NBITS_LO_c : POSITIVE := 17;
465 CONSTANT NBITS_HI_c : POSITIVE := 32 -NBITS_LO_c;
466 VARIABLE tmp_lo_v : STD_LOGIC_VECTOR (NBITS_LO_c +1 DOWNTO 0);
467 VARIABLE tmp_hi0_v : STD_LOGIC_VECTOR (NBITS_HI_c +1 DOWNTO 0);
468 VARIABLE tmp_hi1_v : STD_LOGIC_VECTOR (NBITS_HI_c +1 DOWNTO 0);
470 tmp_lo_v := STD_LOGIC_VECTOR( UNSIGNED( '0' & a(NBITS_LO_c -1 DOWNTO 0) & '1' ) +
471 UNSIGNED( '0' & b(NBITS_LO_c -1 DOWNTO 0) & ci ));
472 tmp_hi0_v := STD_LOGIC_VECTOR( UNSIGNED( '0' & a(31 DOWNTO (32 - NBITS_HI_c)) & '1') +
473 UNSIGNED( '0' & b(31 DOWNTO (32 - NBITS_HI_c)) & '0'));
474 tmp_hi1_v := STD_LOGIC_VECTOR( UNSIGNED( '0' & a(31 DOWNTO (32 - NBITS_HI_c)) & '1') +
475 UNSIGNED( '0' & b(31 DOWNTO (32 - NBITS_HI_c)) & '1'));
476 IF (tmp_lo_v(NBITS_LO_c +1) = '0') THEN
477 s := tmp_hi0_v(NBITS_HI_c DOWNTO 1) & tmp_lo_v(NBITS_LO_c DOWNTO 1);
479 s := tmp_hi1_v(NBITS_HI_c DOWNTO 1) & tmp_lo_v(NBITS_LO_c DOWNTO 1);
483 -- PROCEDURE ep_add32 ( a, b : IN STD_LOGIC_VECTOR; ci : IN STD_LOGIC;
484 -- VARIABLE s : OUT STD_LOGIC_VECTOR;
485 -- VARIABLE co : OUT STD_LOGIC ) IS
486 -- VARIABLE tmp_lo_v : STD_LOGIC_VECTOR (a'LENGTH/2 +1 DOWNTO 0);
487 -- VARIABLE tmp_hi0_v : STD_LOGIC_VECTOR (a'LENGTH/2 +1 DOWNTO 0);
488 -- VARIABLE tmp_hi1_v : STD_LOGIC_VECTOR (a'LENGTH/2 +1 DOWNTO 0);
490 -- tmp_lo_v := STD_LOGIC_VECTOR( UNSIGNED( '0' & a(a'LENGTH/2 -1 DOWNTO 0) & '1' ) +
491 -- UNSIGNED( '0' & b(a'LENGTH/2 -1 DOWNTO 0) & ci ));
492 -- tmp_hi0_v := STD_LOGIC_VECTOR( UNSIGNED( '0' & a(a'LENGTH -1 DOWNTO a'LENGTH/2) & '1') +
493 -- UNSIGNED( '0' & b(a'LENGTH -1 DOWNTO a'LENGTH/2) & '0'));
494 -- tmp_hi1_v := STD_LOGIC_VECTOR( UNSIGNED( '0' & a(a'LENGTH -1 DOWNTO a'LENGTH/2) & '1') +
495 -- UNSIGNED( '0' & b(a'LENGTH -1 DOWNTO a'LENGTH/2) & '1'));
496 -- IF (tmp_lo_v(a'LENGTH/2 +1) = '0') THEN
497 -- s := tmp_hi0_v(a'LENGTH/2 DOWNTO 1) & tmp_lo_v(a'LENGTH/2 DOWNTO 1);
498 -- co := tmp_hi0_v(a'LENGTH/2 +1);
500 -- s := tmp_hi1_v(a'LENGTH/2 DOWNTO 1) & tmp_lo_v(a'LENGTH/2 DOWNTO 1);
501 -- co := tmp_hi1_v(a'LENGTH/2 +1);
505 -- Function ef_nbits returns the minimum number of binary bits to represent
507 -- so N = 0,1 NBITS = 1
509 -- N = 4,5,6,7 NBITS = 3
510 -- N = 8..15 NBITS = 4
511 -- N = 16..31 NBITS = 5
514 FUNCTION ef_nbits( value : NATURAL ) RETURN POSITIVE IS
515 VARIABLE temp_v : POSITIVE;
518 FOR i IN 1 TO INTEGER'HIGH LOOP
520 IF (temp_v > value) THEN
527 END PACKAGE BODY mbl_Pkg;