1 ---------------------------------------------------------------------------------
5 -- Description: the Execution (EX) unit for the TUD MB-Lite implementation
7 -- Author: Huib Lincklaen Arriens
8 -- Delft University of Technology
9 -- Faculty EEMCS, Department ME&CE, Circuits and Systems
10 -- Date: September, 2010
12 -- Modified: Septemper, 2013: FSL scratched (Meloun)
13 -- December, 2010: FSL added (Huib)
14 -- June, 2011: added code for MUL and BARREL (Huib)
15 -- Adapted to work with separate fsl_M-
16 -- and fsl_S selectors and automatic
17 -- tumbl<_jtag><_fsl>.vhd generation (Huib)
20 --------------------------------------------------------------------------------
24 USE IEEE.std_logic_1164.all;
25 USE IEEE.numeric_std.all;
29 ----------------------------------------------------------
31 ----------------------------------------------------------
33 USE_HW_MUL_g : BOOLEAN := TRUE;
34 USE_BARREL_g : BOOLEAN := TRUE;
35 COMPATIBILITY_MODE_g : BOOLEAN := FALSE
38 ID2EX_i : IN ID2EX_Type;
39 GPRF2EX_i : IN GPRF2EX_Type;
40 EX2IF_o : OUT EX2IF_Type;
41 EX2CTRL_o : OUT EX2CTRL_Type;
42 HALT_o : OUT HALT_Type;
44 EX_WRB_i : IN WRB_Type;
45 EX_WRB_o : OUT WRB_Type;
46 MEM_WRB_i : IN WRB_Type;
48 HAZARD_WRB_i : IN HAZARD_WRB_Type;
49 HAZARD_WRB_o : OUT HAZARD_WRB_Type;
51 IMM_LOCK_i : IN IMM_LOCK_Type;
52 IMM_LOCK_o : OUT IMM_LOCK_Type;
57 EX2MEM_o : OUT EX2MEM_Type
62 ----------------------------------------------------------
63 ARCHITECTURE rtl OF exeq IS
64 ----------------------------------------------------------
69 PROCESS (ID2EX_i, GPRF2EX_i, EX_WRB_i, MEM_WRB_i,
70 IMM_LOCK_i, MSR_i, HAZARD_WRB_i)
72 -- function needed by BSLL (only if USE_BARREL_g = TRUE)
73 FUNCTION reverse_bits ( word32 : STD_LOGIC_VECTOR (31 DOWNTO 0) )
74 RETURN STD_LOGIC_VECTOR IS
75 VARIABLE reversed_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
79 reversed_v(31-i) := word32(i);
84 VARIABLE data_rA_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
85 VARIABLE data_rB_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
86 VARIABLE data_rD_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
87 VARIABLE in1_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
88 VARIABLE in2_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
89 VARIABLE hi16_v : STD_LOGIC_VECTOR (15 DOWNTO 0);
90 VARIABLE IMM32_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
91 VARIABLE carry_i_v : STD_LOGIC;
92 VARIABLE result_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
93 VARIABLE carry_o_v : STD_LOGIC;
94 VARIABLE isZero_v : STD_LOGIC;
95 VARIABLE cmpResZero_v : STD_LOGIC;
96 VARIABLE signBit_in1_v : STD_LOGIC;
97 VARIABLE signBit_in2_v : STD_LOGIC;
98 VARIABLE signBit_rA_v : STD_LOGIC;
99 VARIABLE signBit_rD_v : STD_LOGIC;
100 VARIABLE rA_eq_ex_rD_v : STD_LOGIC;
101 VARIABLE rB_eq_ex_rD_v : STD_LOGIC;
102 VARIABLE hazard_v : STD_LOGIC;
103 VARIABLE save_rX_v : SAVE_REG_Type;
104 VARIABLE data_rX_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
105 VARIABLE do_branch_v : STD_LOGIC;
106 VARIABLE byte_Enable_v : STD_LOGIC_VECTOR ( 3 DOWNTO 0);
107 VARIABLE tmp64_v : STD_LOGIC_VECTOR (63 DOWNTO 0);
108 VARIABLE padVec_v : STD_LOGIC_VECTOR (15 DOWNTO 0);
109 VARIABLE halt_v : STD_LOGIC;
110 VARIABLE halt_code_v : STD_LOGIC_VECTOR ( 4 DOWNTO 0);
111 VARIABLE do_cmp_cond_v : STD_LOGIC;
112 VARIABLE cmp_cond_type_v : CMP_COND_TYPE_Type;
116 rA_eq_ex_rD_v := '0';
117 rB_eq_ex_rD_v := '0';
119 save_rX_v := NO_SAVE;
120 data_rX_v := data_rB_v; -- default value for data_rX_v
121 result_v := (OTHERS => '0');
124 byte_Enable_v := "0000";
126 halt_code_v := "00000";
127 do_cmp_cond_v := '0';
128 cmp_cond_type_v := COND_TYPE_ALL;
131 -- create some helper variables
132 IF (ID2EX_i.rdix_rA = EX_WRB_i.wrix_rD) THEN
133 rA_eq_ex_rD_v := '1';
135 IF (ID2EX_i.rdix_rB = EX_WRB_i.wrix_rD) THEN
136 rB_eq_ex_rD_v := '1';
138 -- test where to obtain data_rA from
139 IF ((EX_WRB_i.wrb_Action = WRB_EX) AND (rA_eq_ex_rD_v = '1')) THEN
140 data_rA_v := EX_WRB_i.data_rD;
141 ELSIF ((MEM_WRB_i.wrb_Action /= NO_WRB) AND (ID2EX_i.rdix_rA = MEM_WRB_i.wrix_rD)) THEN
142 data_rA_v := MEM_WRB_i.data_rD;
143 ELSIF ((HAZARD_WRB_i.hazard = '1') AND (HAZARD_WRB_i.save_rX = SAVE_RA)) THEN
144 data_rA_v := HAZARD_WRB_i.data_rX;
146 data_rA_v := GPRF2EX_i.data_rA;
148 -- test where to obtain data_rB from
149 IF ((EX_WRB_i.wrb_Action = WRB_EX) AND (rB_eq_ex_rD_v = '1')) THEN
150 data_rB_v := EX_WRB_i.data_rD;
151 ELSIF ((MEM_WRB_i.wrb_Action /= NO_WRB) AND (ID2EX_i.rdix_rB = MEM_WRB_i.wrix_rD)) THEN
152 data_rB_v := MEM_WRB_i.data_rD;
153 ELSIF ((HAZARD_WRB_i.hazard = '1') AND (HAZARD_WRB_i.save_rX = SAVE_RB)) THEN
154 data_rB_v := HAZARD_WRB_i.data_rX;
156 data_rB_v := GPRF2EX_i.data_rB;
158 -- .... or, isn't all necessary data available yet being still in the pipeline ?
159 data_rX_v := data_rB_v; -- default value for data_rX_v
160 IF (EX_WRB_i.wrb_Action = WRB_MEM) THEN
161 IF ((rA_eq_ex_rD_v = '1') OR (rB_eq_ex_rD_v = '1')) THEN
163 -- always?? IF (MEM_WRB_i.wrb_Action = WRB_MEM) THEN
164 -- handle situations in which both rA and rB needed
165 IF (rA_eq_ex_rD_v = '1') THEN
166 save_rX_v := SAVE_RB; -- already by default data_rX_v = data_rB_v
168 save_rX_v := SAVE_RA;
169 data_rX_v := data_rA_v;
175 IF (IMM_LOCK_i.locked = '1') THEN
176 hi16_v := IMM_LOCK_i.IMM_hi16;
177 ELSIF (ID2EX_i.IMM16(15) = '0') THEN
178 hi16_v := C_16_ZEROS;
182 IMM32_v := hi16_v & ID2EX_i.IMM16;
184 CASE ID2EX_i.alu_Op1 IS
185 WHEN ALU_IN_REGA => in1_v := data_rA_v;
186 WHEN ALU_IN_NOT_REGA => in1_v := NOT data_rA_v;
187 WHEN ALU_IN_PC => in1_v := ID2EX_i.program_counter;
188 WHEN ALU_IN_ZERO => in1_v := C_32_ZEROS;
192 CASE ID2EX_i.alu_Op2 IS
193 WHEN ALU_IN_REGB => in2_v := data_rB_v;
194 WHEN ALU_IN_NOT_REGB => in2_v := NOT data_rB_v;
195 WHEN ALU_IN_IMM => in2_v := IMM32_v;
196 WHEN ALU_IN_NOT_IMM => in2_v := NOT IMM32_v;
200 signBit_in1_v := in1_v(31);
201 signBit_in2_v := in2_v(31);
202 signBit_rA_v := data_rA_v(31);
204 CASE ID2EX_i.alu_Cin IS
205 WHEN CIN_ZERO => carry_i_v := '0';
206 WHEN CIN_ONE => carry_i_v := '1';
207 WHEN FROM_MSR => carry_i_v := MSR_i.C;
208 WHEN FROM_IN1 => carry_i_v := in1_v(31);
209 WHEN OTHERS => carry_i_v := '0';
212 IF (data_rA_v = C_32_ZEROS) THEN
218 CASE ID2EX_i.alu_Action IS
219 WHEN A_ADD | A_CMP | A_CMPU =>
220 ep_add32 ( in1_v, in2_v, carry_i_v, result_v, carry_o_v);
221 IF (id2ex_i.alu_Action = A_CMPU) THEN
222 IF (signBit_in1_v = signBit_in2_v) THEN
223 signBit_rD_v := NOT signBit_in1_v;
225 ELSIF (id2ex_i.alu_Action = A_CMP) THEN
226 IF (signBit_in1_v = signBit_in2_v) THEN
227 signBit_rD_v := signBit_in1_v;
231 result_v(31) := signBit_rD_v;
233 IF (COMPATIBILITY_MODE_g = FALSE) THEN
234 IF (ID2EX_i.cmp_Cond /= COND_ALL) THEN
235 IF (result_v = C_32_ZEROS) THEN
241 CASE ID2EX_i.cmp_Cond IS
242 WHEN COND_EQ => do_cmp_cond_v := cmpResZero_v;
243 WHEN COND_NE => do_cmp_cond_v := NOT cmpResZero_v;
244 WHEN COND_LT => do_cmp_cond_v := signBit_rD_v;
245 WHEN COND_LE => do_cmp_cond_v := signBit_rD_v OR cmpResZero_v;
246 WHEN COND_GT => do_cmp_cond_v := NOT (signBit_rD_v OR cmpResZero_v);
247 WHEN COND_GE => do_cmp_cond_v := NOT signBit_rD_v;
251 cmp_cond_type_v := ID2EX_i.cmp_Cond_Type;
256 result_v := in1_v OR in2_v;
258 result_v := in1_v AND in2_v;
260 result_v := in1_v XOR in2_v;
262 result_v := carry_i_v & in1_v(31 DOWNTO 1);
263 carry_o_v := in1_v(0);
265 IF (in1_v(7) = '0') THEN
266 result_v := C_24_ZEROS & in1_v( 7 DOWNTO 0);
268 result_v := C_24_ONES & in1_v( 7 DOWNTO 0);
271 IF (in1_v(15) = '0') THEN
272 result_v := C_16_ZEROS & in1_v(15 DOWNTO 0);
274 result_v := C_16_ONES & in1_v(15 DOWNTO 0);
277 result_v := MSR_i.C & C_24_ZEROS & "0000" & MSR_i.C & MSR_i.IE & '0';
279 MSR_o.IE <= data_Ra_v(1);
280 MSR_o.C <= data_Ra_v(2);
282 IF (USE_HW_MUL_g = TRUE) THEN
283 tmp64_v := STD_LOGIC_VECTOR( UNSIGNED(in1_v) * UNSIGNED(in2_v) );
284 result_v := tmp64_v(31 DOWNTO 0);
286 WHEN A_BSLL | A_BSRL | A_BSRA =>
287 IF (USE_BARREL_g = TRUE) THEN
288 IF (ID2EX_i.alu_Action = A_BSLL) THEN
289 result_v := reverse_bits (in1_v);
293 IF (ID2EX_i.alu_Action = A_BSRA) THEN
294 padVec_v := (OTHERS => in1_v(31));
296 padVec_v := (OTHERS => '0');
298 IF (in2_v(4) = '1') THEN
299 result_v := padVec_v (15 DOWNTO 0) & result_v (31 DOWNTO 16);
301 IF (in2_v(3) = '1') THEN
302 result_v := padVec_v ( 7 DOWNTO 0) & result_v (31 DOWNTO 8);
304 IF (in2_v(2) = '1') THEN
305 result_v := padVec_v ( 3 DOWNTO 0) & result_v (31 DOWNTO 4);
307 IF (in2_v(1) = '1') THEN
308 result_v := padVec_v ( 1 DOWNTO 0) & result_v (31 DOWNTO 2);
310 IF (in2_v(0) = '1') THEN
311 result_v := padVec_v ( 0 DOWNTO 0) & result_v (31 DOWNTO 1);
313 IF (ID2EX_i.alu_Action = A_BSLL) THEN
314 result_v := reverse_bits (result_v);
316 END IF; -- (USE_BARREL_g = TRUE)
319 halt_code_v := ID2EX_i.IMM16(4 DOWNTO 0);
324 CASE ID2EX_i.branch_Action IS
325 WHEN BR => do_branch_v := '1';
326 WHEN BRL => do_branch_v := '1';
327 WHEN BEQ => do_branch_v := isZero_v;
328 WHEN BNE => do_branch_v := NOT isZero_v;
329 WHEN BLT => do_branch_v := signBit_rA_v;
330 WHEN BLE => do_branch_v := signBit_rA_v OR isZero_v;
331 WHEN BGT => do_branch_v := NOT (signBit_rA_v OR isZero_v);
332 WHEN BGE => do_branch_v := NOT signBit_rA_v;
335 IF (do_branch_v = '1') THEN
336 EX2IF_o.take_branch <= '1';
337 EX2IF_o.branch_target <= result_v;
339 EX2IF_o.take_branch <= '0';
340 EX2IF_o.branch_target <= C_32_ZEROS;
344 IF (COMPATIBILITY_MODE_g = FALSE) THEN
345 CASE cmp_cond_type_v IS
346 WHEN COND_TYPE_ALL =>
347 EX2CTRL_o.flush_first <= '0';
348 EX2CTRL_o.flush_second <= '0';
349 WHEN COND_TYPE_IF_THEN =>
350 EX2CTRL_o.flush_first <= not do_cmp_cond_v;
351 EX2CTRL_o.flush_second <= '0';
352 WHEN COND_TYPE_IF_THEN_THEN =>
353 EX2CTRL_o.flush_first <= not do_cmp_cond_v;
354 EX2CTRL_o.flush_second <= not do_cmp_cond_v;
355 WHEN COND_TYPE_IF_THEN_ELSE =>
356 EX2CTRL_o.flush_first <= not do_cmp_cond_v;
357 EX2CTRL_o.flush_second <= do_cmp_cond_v;
364 HALT_o.halt <= halt_v;
365 HALT_o.halt_code <= halt_code_v;
367 -- WR_MEM/RD_MEM: result_v --> exeq_result --> mem_address,
368 -- WR_MEM: data_rD --> data_out_to_mem
369 -- BRL: prog_counter --> exeq_result
370 -- else result_v --> exeq_result (data_rD not used)
371 EX2MEM_o.wrix_rD <= ID2EX_i.curr_rD;
372 IF (ID2EX_i.branch_Action = BRL) THEN
373 EX2MEM_o.wrb_Action <= WRB_EX;
374 EX2MEM_o.exeq_result <= ID2EX_i.program_counter;
375 EX2MEM_o.data_rD <= ID2EX_i.program_counter;
376 -- set data_rD_v, although unused, to prevent an inferred latch
377 data_rD_v := GPRF2EX_i.data_rD;
379 EX2MEM_o.wrb_Action <= ID2EX_i.wrb_Action;
380 EX2MEM_o.exeq_result <= result_v;
381 -- test where to obtain data_rD from
382 IF (HAZARD_WRB_i.hazard = '1') THEN
383 data_rD_v := HAZARD_WRB_i.data_rD;
384 ELSIF ((EX_WRB_i.wrb_Action = WRB_EX) AND (ID2EX_i.curr_rD = EX_WRB_i.wrix_rD)) THEN
385 -- forward rD_data just calculated, to handle e.g. addi rD,rA,Imm; sw rD,mem[y]; ...
386 data_rD_v := EX_WRB_i.data_rD;
387 ELSIF ((MEM_WRB_i.wrb_Action /= NO_WRB) AND (ID2EX_i.curr_rD = MEM_WRB_i.wrix_rD)) THEN
388 data_rD_v := MEM_WRB_i.data_rD;
390 data_rD_v := GPRF2EX_i.data_rD;
393 IF (ID2EX_i.mem_Action /= NO_MEM) THEN
394 CASE ID2EX_i.transfer_Size IS
396 CASE result_v( 1 DOWNTO 0) IS
397 WHEN "00" => byte_Enable_v := "1000";
398 WHEN "01" => byte_Enable_v := "0100";
399 WHEN "10" => byte_Enable_v := "0010";
400 WHEN "11" => byte_Enable_v := "0001";
404 CASE result_v( 1 DOWNTO 0) IS
405 WHEN "00" => byte_Enable_v := "1100";
406 WHEN "10" => byte_Enable_v := "0011";
409 WHEN OTHERS => byte_Enable_v := "1111";
413 -- update MSR[IE] and/or MSR[C] if needed
414 IF (ID2EX_i.alu_Action /= A_MTS) THEN
415 MSR_o.IE <= MSR_i.IE;
416 IF (ID2EX_i.msr_Action = UPDATE_CARRY) THEN
417 MSR_o.C <= carry_o_v;
423 -- pass remaining data to mem
424 EX2MEM_o.mem_Action <= ID2EX_i.mem_Action;
425 EX2MEM_o.data_rD <= data_rD_v;
426 EX2MEM_o.byte_Enable <= byte_Enable_v;
427 EX2MEM_o.wrix_rD <= ID2EX_i.curr_rD;
429 IMM_LOCK_o.locked <= ID2EX_i.IMM_Lock;
430 IMM_LOCK_o.IMM_hi16 <= ID2EX_i.IMM16;
432 EX_WRB_o.wrb_Action <= ID2EX_i.wrb_Action;
433 EX_WRB_o.wrix_rD <= ID2EX_i.curr_rD;
434 EX_WRB_o.data_rD <= result_v;
436 HAZARD_WRB_o.hazard <= hazard_v;
437 HAZARD_WRB_o.save_rX <= save_rX_v;
438 HAZARD_WRB_o.data_rX <= data_rX_v;
439 HAZARD_WRB_o.data_rD <= data_rD_v;
443 END ARCHITECTURE rtl;