use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-use work.mbl_pkg.all;
-use work.lx_rocon_pkg.all;
+use work.lx_fncapprox_pkg.all;
-- IRC bus interconnect
entity lx_fncapprox is
);
end lx_fncapprox;
+-- reciproc ... a - (b - c * x) * x
+-- sin ... a + (b - c * x) * x
+
+
architecture Behavioral of lx_fncapprox is
- component rom_table
- generic
- (
- data_width : integer;
- addr_width : integer;
- init_file : string
- );
- port
- (
- ack_o : out std_logic;
- addr_i : in std_logic_vector (addr_width-1 downto 0);
- clk_i : in std_logic;
- data_o : out std_logic_vector (data_width-1 downto 0);
- stb_i : in std_logic
- );
- end component;
+ -- Types
+
+ type state_fncapprox_t is (ST_IDLE, ST_RECI0, ST_RECI1,
+ ST_SIN0, ST_SIN1, ST_COS0, ST_COS1);
+
+ -- Signals
- constant approx_tab_bits : natural := 8;
+ constant approx_top_bits : natural := 9;
+ constant reci_tab_bits : natural := 8;
+ constant sin_tab_bits : natural := 7;
constant approx_frac_bits : natural := 18;
+ constant approx_tab_b_shift : natural := 9;
+ constant approx_tab_c_shift : natural := 25;
- constant reci_tab_b_shift : natural := 9;
- constant reci_tab_c_shift : natural := 25;
+ constant approx_lo_used_bit : natural := 31 - approx_top_bits - approx_frac_bits + 1;
signal ce_s : std_logic;
+ signal address_s : std_logic_vector(4 downto 0);
+
+ signal argument_s : std_logic_vector(31 downto 0);
+ signal argument_r : std_logic_vector(31 downto 0);
+
+ signal dsp48_p_s : std_logic_vector(47 downto 0);
+ signal dsp48_a_s : std_logic_vector(17 downto 0);
+ signal dsp48_b_s : std_logic_vector(17 downto 0);
+ signal dsp48_c_s : std_logic_vector(47 downto 0);
+ signal dsp48_add_sub_x_s : std_logic;
+ signal dsp48_ce_s : std_logic;
+
+ signal state_tab_s : state_fncapprox_t;
+ signal state_tab_r : state_fncapprox_t;
+ signal state_dsp48_r : state_fncapprox_t;
+ signal state_regw_r : state_fncapprox_t;
- signal approx_tab_idx_s : std_logic_vector(approx_tab_bits-1 downto 0);
- signal approx_tab_idx_r : std_logic_vector(approx_tab_bits-1 downto 0);
+ signal reci_tab_idx_s : std_logic_vector(reci_tab_bits-1 downto 0);
signal approx_frac_s : std_logic_vector(approx_frac_bits-1 downto 0);
signal approx_frac_r : std_logic_vector(approx_frac_bits-1 downto 0);
signal reci_tab_a_data_s : std_logic_vector(35 downto 0);
signal reci_tab_bc_data_s : std_logic_vector(35 downto 0);
signal reci_tab_bc_data_r : std_logic_vector(35 downto 0);
- signal reci_tab_b_shifted_r : std_logic_vector(47 downto 0);
+ signal sin_tab_idx_s : std_logic_vector(sin_tab_bits-1 downto 0);
+ signal sin_tab_a_data_s : std_logic_vector(35 downto 0);
+ signal sin_tab_bc_data_s : std_logic_vector(35 downto 0);
+
+ signal approx_tab_b_shifted_r : std_logic_vector(47 downto 0);
signal reci_tab_a_shifted_r : std_logic_vector(47 downto 0);
signal frac_c_mult_s : std_logic_vector(47 downto 0);
signal frac2_bc_mult_s : std_logic_vector(47 downto 0);
- signal approx_result_s : std_logic_vector(31 downto 0);
+ signal reci_result_s : std_logic_vector(31 downto 0);
+ signal reci_result_r : std_logic_vector(31 downto 0);
+ signal sin_result_s : std_logic_vector(31 downto 0);
+ signal sin_result_r : std_logic_vector(31 downto 0);
+ signal cos_result_s : std_logic_vector(31 downto 0);
+ signal cos_result_r : std_logic_vector(31 downto 0);
- signal reci_tab_a_ack_s : std_logic;
- signal reci_tab_a_ack_r : std_logic;
signal reci_tab_a_stb_s : std_logic;
-
- signal reci_tab_bc_ack_s : std_logic;
- signal reci_tab_bc_ack_r : std_logic;
signal reci_tab_bc_stb_s : std_logic;
+ signal sin_tab_a_stb_s : std_logic;
+ signal sin_tab_bc_stb_s : std_logic;
+
+ signal sin_cos_force_one_s : std_logic;
+ signal sin_cos_force_one_r : std_logic;
+ signal sin_cos_force_one_r2 : std_logic;
+ signal sin_cos_negate_out_s : std_logic;
+ signal sin_cos_negate_out_r : std_logic;
+ signal sin_cos_negate_out_r2: std_logic;
begin
+approx_dsp48: lx_fncapprox_dsp48
+ port map (
+ P => dsp48_p_s,
+ A => dsp48_a_s,
+ B => dsp48_b_s,
+ C => dsp48_c_s,
+ ADD_SUB_X => dsp48_add_sub_x_s,
+ CLK => clk_i,
+ CE => dsp48_ce_s
+ );
+
reci_tab_a : rom_table
generic map (
data_width => 36,
- addr_width => approx_tab_bits,
+ addr_width => reci_tab_bits,
init_file => "reci_tab_a.lut"
)
port map
(
clk_i => clk_i,
stb_i => reci_tab_a_stb_s,
- addr_i => approx_tab_idx_s,
- data_o => reci_tab_a_data_s,
- ack_o => reci_tab_a_ack_s
+ addr_i => reci_tab_idx_s,
+ data_o => reci_tab_a_data_s
);
reci_tab_bc : rom_table
generic map (
data_width => 36,
- addr_width => approx_tab_bits,
+ addr_width => reci_tab_bits,
init_file => "reci_tab_bc.lut"
)
port map
(
clk_i => clk_i,
stb_i => reci_tab_bc_stb_s,
- addr_i => approx_tab_idx_s,
- data_o => reci_tab_bc_data_s,
- ack_o => reci_tab_bc_ack_s
+ addr_i => reci_tab_idx_s,
+ data_o => reci_tab_bc_data_s
);
-wire_in:
- process(next_ce_i, ce_s, bls_i, address_i, data_i, approx_tab_idx_r, approx_frac_r)
+sin_tab_a : rom_table
+ generic map (
+ data_width => 36,
+ addr_width => sin_tab_bits,
+ init_file => "sin_tab_a.lut"
+ )
+ port map
+ (
+ clk_i => clk_i,
+ stb_i => sin_tab_a_stb_s,
+ addr_i => sin_tab_idx_s,
+ data_o => sin_tab_a_data_s
+ );
+
+sin_tab_bc : rom_table
+ generic map (
+ data_width => 36,
+ addr_width => sin_tab_bits,
+ init_file => "sin_tab_bc.lut"
+ )
+ port map
+ (
+ clk_i => clk_i,
+ stb_i => sin_tab_bc_stb_s,
+ addr_i => sin_tab_idx_s,
+ data_o => sin_tab_bc_data_s
+ );
+
+wire_in_and_next_state:
+ process(next_ce_i, ce_s, bls_i, address_i, data_i, state_tab_r, argument_r)
+ begin
+ -- Incoming bus request
+ if (next_ce_i = '1') and (bls_i(0) = '1') then
+ argument_s <= data_i;
+ if address_i(4 downto 0) = "00001" then
+ state_tab_s <= ST_RECI0;
+ elsif address_i(4 downto 0) = "00010" then
+ state_tab_s <= ST_SIN0;
+ elsif address_i(4 downto 0) = "00011" then
+ state_tab_s <= ST_COS0;
+ else
+ state_tab_s <= ST_IDLE;
+ end if;
+ else
+ argument_s <= argument_r;
+ case state_tab_r is
+ when ST_IDLE =>
+ state_tab_s <= ST_IDLE;
+ when ST_RECI0 =>
+ state_tab_s <= ST_RECI1;
+ when ST_RECI1 =>
+ state_tab_s <= ST_IDLE;
+ when ST_SIN0 =>
+ state_tab_s <= ST_SIN1;
+ when ST_SIN1 =>
+ state_tab_s <= ST_COS0;
+ when ST_COS0 =>
+ state_tab_s <= ST_COS1;
+ when ST_COS1 =>
+ state_tab_s <= ST_IDLE;
+ end case;
+ end if;
+ end process;
+
+function_tables_access:
+ process(state_tab_r, argument_r)
+ variable negate_arg_v : std_logic;
+ variable arg_frac_is_zeros_v : std_logic;
begin
-- init values
- reci_tab_a_stb_s <= '0';
- reci_tab_bc_stb_s <= '0';
- approx_tab_idx_s <= approx_tab_idx_r;
- approx_frac_s <= approx_frac_r;
+ reci_tab_idx_s <= (others => '-');
+ sin_tab_idx_s <= (others => '-');
+ approx_frac_s <= (others => '-');
+ sin_cos_force_one_s <= '-';
+ sin_cos_negate_out_s <= '-';
- -- Incoming bus request
- if next_ce_i = '1' then
- if bls_i(0) = '1' then
- reci_tab_a_stb_s <= '1';
+ negate_arg_v := '-';
+
+ reci_tab_a_stb_s <= '0';
+ reci_tab_bc_stb_s <= '0';
+ sin_tab_a_stb_s <= '0';
+ sin_tab_bc_stb_s <= '0';
+
+ if argument_r(29 downto approx_lo_used_bit) = (28 - approx_lo_used_bit downto 0 => '0') then
+ arg_frac_is_zeros_v := '1';
+ else
+ arg_frac_is_zeros_v := '0';
+ end if;
+
+ case state_tab_r is
+ when ST_IDLE =>
+ null;
+
+ when ST_RECI0 =>
+ reci_tab_idx_s <= argument_r(30 downto
+ 30 - reci_tab_bits + 1);
reci_tab_bc_stb_s <= '1';
- approx_tab_idx_s <= data_i(30 downto
- 30 - approx_tab_bits + 1);
- approx_frac_s <= data_i(30 - approx_tab_bits downto
- 30 - approx_tab_bits - approx_frac_bits + 1);
- end if;
+ negate_arg_v := '0';
+
+ when ST_RECI1 =>
+ reci_tab_idx_s <= argument_r(30 downto
+ 30 - reci_tab_bits + 1);
+ reci_tab_a_stb_s <= '1';
+ negate_arg_v := '0';
+
+ when ST_SIN0 =>
+ sin_tab_bc_stb_s <= '1';
+ sin_tab_a_stb_s <= '1';
+ negate_arg_v := argument_r(30);
+
+ when ST_SIN1 =>
+ if (arg_frac_is_zeros_v = '1') and (argument_r(30) = '1') then
+ sin_cos_force_one_s <= '1';
+ else
+ sin_cos_force_one_s <= '0';
+ end if;
+
+ if argument_r(31) = '1' then
+ sin_cos_negate_out_s <= '1';
+ else
+ sin_cos_negate_out_s <= '0';
+ end if;
+
+ sin_tab_bc_stb_s <= '1';
+ negate_arg_v := argument_r(30);
+
+ when ST_COS0 =>
+ sin_tab_bc_stb_s <= '1';
+ sin_tab_a_stb_s <= '1';
+ negate_arg_v := not argument_r(30);
+
+ when ST_COS1 =>
+ if (arg_frac_is_zeros_v = '1') and (argument_r(30) = '0') then
+ sin_cos_force_one_s <= '1';
+ else
+ sin_cos_force_one_s <= '0';
+ end if;
+
+ if argument_r(31) /= argument_r(30) then
+ sin_cos_negate_out_s <= '1';
+ else
+ sin_cos_negate_out_s <= '0';
+ end if;
+
+ sin_tab_bc_stb_s <= '1';
+ negate_arg_v := not argument_r(30);
+ end case;
+
+ if negate_arg_v = '0' then
+ sin_tab_idx_s <= argument_r(29 downto
+ 29 - sin_tab_bits + 1);
+ approx_frac_s <= argument_r(31 - approx_top_bits downto
+ 31 - approx_top_bits - approx_frac_bits + 1);
+ else
+ sin_tab_idx_s <= not argument_r(29 downto
+ 29 - sin_tab_bits + 1);
+ approx_frac_s <= not argument_r(31 - approx_top_bits downto
+ 31 - approx_top_bits - approx_frac_bits + 1);
end if;
end process;
-wire_out:
- process(ce_s, approx_result_s)
+dsp48_computation:
+ process(state_dsp48_r, approx_frac_r, dsp48_p_s,
+ reci_tab_a_data_s, reci_tab_bc_data_s,
+ sin_tab_a_data_s, sin_tab_bc_data_s)
+ begin
+ dsp48_a_s <= (others => '-');
+ dsp48_b_s <= (others => '-');
+ dsp48_c_s <= (others => '-');
+ dsp48_add_sub_x_s <= '-';
+ dsp48_ce_s <= '0';
+
+ case state_dsp48_r is
+ when ST_IDLE =>
+ null;
+
+ when ST_RECI0 =>
+ -- yl = reci_tab_a[ti];
+ -- yl -= ((reci_tab_b[ti] - ((reci_tab_c[ti] * xd) >> approx_tab_c_shift)) * xd) >> approx_tab_b_shift;
+
+ dsp48_c_s(approx_tab_c_shift - 1 downto 0) <= (others => '0');
+ dsp48_c_s(approx_tab_c_shift + 17 downto approx_tab_c_shift) <= reci_tab_bc_data_s(35 downto 18);
+ dsp48_c_s(47 downto approx_tab_c_shift + 18) <= (others => '0');
+
+ dsp48_a_s <= reci_tab_bc_data_s(17 downto 0);
+ dsp48_b_s <= approx_frac_r;
+ dsp48_add_sub_x_s <= '1';
+ dsp48_ce_s <= '1';
+
+ when ST_RECI1 =>
+ dsp48_c_s(approx_tab_b_shift - 1 downto 0) <= (others => '0');
+ dsp48_c_s(approx_tab_b_shift + 35 downto approx_tab_b_shift) <= reci_tab_a_data_s;
+ dsp48_c_s(47 downto approx_tab_b_shift + 36) <= (others => '0');
+
+ dsp48_a_s <= dsp48_p_s(approx_tab_c_shift + 17 downto approx_tab_c_shift);
+ dsp48_b_s <= approx_frac_r;
+ dsp48_add_sub_x_s <= '1';
+ dsp48_ce_s <= '1';
+
+ when ST_SIN0 | ST_COS0 =>
+ dsp48_c_s(approx_tab_c_shift - 1 downto 0) <= (others => '0');
+ dsp48_c_s(approx_tab_c_shift + 17 downto approx_tab_c_shift) <= sin_tab_bc_data_s(35 downto 18);
+ dsp48_c_s(47 downto approx_tab_c_shift + 18) <= (others => '0');
+
+ dsp48_a_s <= sin_tab_bc_data_s(17 downto 0);
+ dsp48_b_s <= approx_frac_r;
+ dsp48_add_sub_x_s <= '1';
+ dsp48_ce_s <= '1';
+
+ when ST_SIN1 | ST_COS1 =>
+ dsp48_c_s(approx_tab_b_shift - 1 downto 0) <= (others => '0');
+ dsp48_c_s(approx_tab_b_shift + 35 downto approx_tab_b_shift) <= sin_tab_a_data_s;
+ dsp48_c_s(47 downto approx_tab_b_shift + 36) <= (others => '0');
+
+ dsp48_a_s <= dsp48_p_s(approx_tab_c_shift + 17 downto approx_tab_c_shift);
+ dsp48_b_s <= approx_frac_r;
+ dsp48_add_sub_x_s <= '0';
+ dsp48_ce_s <= '1';
+
+ end case;
+ end process;
+
+result_registers_write:
+ process(state_regw_r, dsp48_p_s, sin_cos_negate_out_r2, sin_cos_force_one_r2,
+ reci_result_r, sin_result_r, cos_result_r)
+ variable sin_cos_res_v : std_logic_vector(31 downto 0);
begin
+ reci_result_s <= reci_result_r;
+ sin_result_s <= sin_result_r;
+ cos_result_s <= cos_result_r;
+
+ if sin_cos_force_one_r2 = '1' then
+ sin_cos_res_v := (30 => '1', others => '0');
+ else
+ sin_cos_res_v := dsp48_p_s(approx_tab_b_shift + 35 -1 downto approx_tab_b_shift + 4 - 1);
+ end if;
+
+ if sin_cos_negate_out_r2 = '1' then
+ sin_cos_res_v := std_logic_vector(-signed(sin_cos_res_v));
+ end if;
+
+ case state_regw_r is
+ when ST_IDLE =>
+ null;
+
+ when ST_RECI0 =>
+ null;
+
+ when ST_RECI1 =>
+ reci_result_s <= dsp48_p_s(approx_tab_b_shift + 35 downto approx_tab_b_shift + 4);
+
+ when ST_SIN0 =>
+ null;
+
+ when ST_SIN1 =>
+ sin_result_s <= sin_cos_res_v;
+
+ when ST_COS0 =>
+ null;
- data_o <= (others => '0');
+ when ST_COS1 =>
+ cos_result_s <= sin_cos_res_v;
+
+ end case;
+ end process;
+
+wire_out:
+ process(ce_s, reci_result_r, sin_result_r, cos_result_r, address_s, argument_r)
+ begin
+ data_o <= (others => '-');
if ce_s = '1' then
- data_o <= approx_result_s;
+ if address_s(4 downto 0) = "00000" then
+ data_o <= x"12345678";
+ elsif address_s(4 downto 0) = "00001" then
+ data_o <= reci_result_r;
+ elsif address_s(4 downto 0) = "00010" then
+ data_o <= sin_result_r;
+ elsif address_s(4 downto 0) = "00011" then
+ data_o <= cos_result_r;
+ elsif address_s(4 downto 0) = "00100" then
+ data_o(17 downto 0) <= sin_result_r(31 downto 14);
+ data_o(31 downto 18) <= (others => sin_result_r(31));
+ elsif address_s(4 downto 0) = "00101" then
+ data_o(17 downto 0) <= cos_result_r(31 downto 14);
+ data_o(31 downto 18) <= (others => cos_result_r(31));
+ elsif address_s(4 downto 0) = "00110" then
+ data_o <= x"ABCDEF01";
+ elsif address_s(4 downto 0) = "00111" then
+ data_o <= argument_r;
+ else
+ data_o <= (others => '0');
+ end if;
end if;
end process;
begin
wait until clk_i'event and clk_i= '1';
ce_s <= next_ce_i;
- if reci_tab_a_ack_s = '1' then
- reci_tab_a_data_r <= reci_tab_a_data_s;
- end if;
- if reci_tab_bc_ack_s = '1' then
- reci_tab_bc_data_r <= reci_tab_bc_data_s;
- end if;
-
- -- yl = reci_tab_a[ti];
- -- yl -= ((reci_tab_b[ti] - ((reci_tab_c[ti] * xd) >> RECI_TAB_C_SHIFT)) * xd) >> RECI_TAB_B_SHIFT;
-
- reci_tab_b_shifted_r(reci_tab_c_shift - 1 downto 0) <= (others => '0');
- reci_tab_b_shifted_r(reci_tab_c_shift + 17 downto reci_tab_c_shift) <= reci_tab_bc_data_r(35 downto 18);
- reci_tab_b_shifted_r(47 downto reci_tab_c_shift + 18) <= (others => '0');
-
- frac_c_mult_s <= std_logic_vector(unsigned(reci_tab_b_shifted_r) -
- (unsigned(reci_tab_bc_data_r(17 downto 0)) * unsigned(approx_frac_r)));
+ address_s <= address_i;
- reci_tab_a_shifted_r(reci_tab_b_shift - 1 downto 0) <= (others => '0');
- reci_tab_a_shifted_r(reci_tab_b_shift + 35 downto reci_tab_b_shift) <= reci_tab_a_data_r;
- reci_tab_a_shifted_r(47 downto reci_tab_b_shift + 36) <= (others => '0');
+ approx_frac_r <= approx_frac_s;
- frac2_bc_mult_s <= std_logic_vector(unsigned(reci_tab_a_shifted_r) -
- unsigned(frac_c_mult_s(reci_tab_c_shift + 17 downto reci_tab_c_shift)) *
- unsigned(approx_frac_r));
+ state_tab_r <= state_tab_s;
+ state_dsp48_r <= state_tab_r;
+ state_regw_r <= state_dsp48_r;
- approx_result_s <= frac2_bc_mult_s(reci_tab_b_shift + 35 downto reci_tab_b_shift + 4);
+ argument_r <= argument_s;
+ sin_cos_force_one_r <= sin_cos_force_one_s;
+ sin_cos_force_one_r2 <= sin_cos_force_one_r;
+ sin_cos_negate_out_r <= sin_cos_negate_out_s;
+ sin_cos_negate_out_r2 <= sin_cos_negate_out_r;
- reci_tab_a_ack_r <= reci_tab_a_ack_s;
- reci_tab_bc_ack_r <= reci_tab_bc_ack_s;
- approx_tab_idx_r <= approx_tab_idx_s;
- approx_frac_r <= approx_frac_s;
+ reci_result_r <= reci_result_s;
+ sin_result_r <= sin_result_s;
+ cos_result_r <= cos_result_s;
end process;
end Behavioral;
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projects / fpga / lx-cpu1 / lx-rocon.git / commitdiff