ROCON GHDL simulation testbed setup for concurrent access bug hunt.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>

diff --git a/hw/tb/Makefile b/hw/tb/Makefile
index b1c93a4829f5adb5a48c5614c40161abc7d0eabe..389c9ad9aef390e58c6df2ec855e67d38f0ed24f 100644 (file)
--- a/hw/tb/Makefile
+++ b/hw/tb/Makefile
@@ -25,7 +25,7 @@ SRC+=lx_tumbl_tb.vhd
 CFLAGS += -Wall
 
 GHDLFLAGS+=
-ANALYZEFLAGS+=--std=93c --ieee=synopsys -fexplicit
+ANALYZEFLAGS+=--std=93c --ieee=synopsys -fexplicit -ggdb
 
 #SIM_FLAGS=--stop-time=1000ns #--ieee-asserts=disable
 
@@ -40,7 +40,7 @@ test-tumbl: analyze-all imem.bits
        $(GHDL) $(GHDLFLAGS) -m $(ANALYZEFLAGS) lx_tumbl_tb
        $(GHDL) $(GHDLFLAGS) -r  lx_tumbl_tb --stop-time=10000ns --vcd=$@.vcd --wave=$@.ghw
 
-test-rocon: analyze-all
+test-rocon: analyze-all imem.bits
        $(GHDL) $(GHDLFLAGS) -m $(ANALYZEFLAGS) lx_rocon_top_tb
        $(GHDL) $(GHDLFLAGS) -r lx_rocon_top_tb --stop-time=10000ns --vcd=$@.vcd --wave=$@.ghw
 

diff --git a/hw/tb/lx_rocon_top_tb.vhd b/hw/tb/lx_rocon_top_tb.vhd
index 00dce29783cde2dcde90c9ed88a3f450fc3dec54..f8e64edb5f8bd193078f993e5964f5c3c29f647e 100644 (file)
--- a/hw/tb/lx_rocon_top_tb.vhd
+++ b/hw/tb/lx_rocon_top_tb.vhd
@@ -1,5 +1,9 @@
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.all;
+
+LIBRARY std;
+USE std.textio.all;
 
 ENTITY lx_rocon_top_tb IS
 END lx_rocon_top_tb;
@@ -194,4 +198,73 @@ BEGIN
       wait;
    end process;
 
+       setup_imem_process : process
+               file imem_file : text open READ_MODE is "imem.bits";
+               variable my_line : LINE;
+               variable bits_line : LINE;
+               variable mem_location : bit_vector(31 downto 0);
+               variable imem_fill_addr : natural range 0 to 2**8-1 := 0;
+       begin
+
+               -- Assert ROCON system reset for 3 clock cycles
+               wait until clk_50m'event and clk_50m = '1';
+               init <= '0';
+               wait until clk_50m'event and clk_50m = '1';
+               wait until clk_50m'event and clk_50m = '1';
+               wait until clk_50m'event and clk_50m = '1';
+               init <= '1';
+
+               -- Fill Tumbl instruction memory
+               fill_loop: while not endfile(imem_file) loop
+                       wait until clk_50m'event and clk_50m = '1';
+                       cs0_xc <= '1';
+                       rd <= '1';
+                       bls <= "1111";
+                       wait until clk_50m'event and clk_50m = '1';
+                       address <= std_logic_vector(to_unsigned(imem_fill_addr, 16));
+                       readline(imem_file, bits_line);
+                       read(bits_line, mem_location);
+                       data <= to_stdLogicVector(mem_location);
+                       bls <= "0000";
+                       cs0_xc <= '0';
+                       imem_fill_addr := imem_fill_addr + 1;
+                       wait until clk_50m'event and clk_50m = '1';
+                       wait until clk_50m'event and clk_50m = '1';
+                       cs0_xc <= '1';
+                       rd <= '1';
+                       bls <= "1111";
+               end loop fill_loop;
+
+               -- Negate Tumbl reset state in Tumbl control register
+               wait until clk_50m'event and clk_50m = '1';
+               wait until clk_50m'event and clk_50m = '1';
+               address <= x"0C00";
+               data <= x"00000000";
+               bls <= "0000";
+               cs0_xc <= '0';
+               wait until clk_50m'event and clk_50m = '1';
+               wait until clk_50m'event and clk_50m = '1';
+               cs0_xc <= '1';
+               rd <= '1';
+               bls <= "1111";
+
+               -- Simulate external master accesses to Tumbl shared xmem bus
+               xmem_loop: loop
+                       wait until clk_50m'event and clk_50m = '1';
+                       wait until clk_50m'event and clk_50m = '1';
+                       address <= x"8808";
+                       rd <= '0';
+                       cs0_xc <= '0';
+                       wait until clk_50m'event and clk_50m = '1';
+                       wait until clk_50m'event and clk_50m = '1';
+                       wait until clk_50m'event and clk_50m = '1';
+                       cs0_xc <= '1';
+                       rd <= '1';
+                       bls <= "1111";
+               end loop xmem_loop;
+
+               wait;
+
+       end process;
+
 END;

diff --git a/hw/tb/lx_tumbl_tb.vhd b/hw/tb/lx_tumbl_tb.vhd
index 66a1652a24d2c338d8ec9a9f7d23a900912aa0af..541863f4cc8b3b9163e3534353d70163c9105bb9 100644 (file)
--- a/hw/tb/lx_tumbl_tb.vhd
+++ b/hw/tb/lx_tumbl_tb.vhd
@@ -51,6 +51,8 @@ ARCHITECTURE behavior OF lx_tumbl_tb IS
 
        -- Simulate special events and interactions
        signal delay_access_s : std_logic := '0';
+       signal delay_access_r : std_logic := '0';
+       signal delay_access_r2 : std_logic := '0';
 
 BEGIN
        -- Instantiate the Unit Under Test (UUT)
@@ -144,16 +146,18 @@ BEGIN
 
        end process;
 
-       events_process: process(cycle_cnt)
+       events_process: process(cycle_cnt, xmemb_sel_s, delay_access_r, delay_access_r2)
        begin
-               -- Enable clken only when available for Tumbl
-               if cycle_cnt >= 34 and cycle_cnt <= 34 then
+               -- Simulate externall access to xmem bus shared with Tumbl
+               if cycle_cnt >= 33 and cycle_cnt <= 33 then
+               -- if xmemb_sel_s = '1' and (delay_access_r = '0' or delay_access_r2 = '0') then
                        delay_access_s <= '1';
                else
                        delay_access_s <= '0';
                end if;
        end process;
 
+       -- Enable xmem clken only when bus available for Tumbl
        xmemb_i_s.clken <= not delay_access_s;
 
        xmemb_process :process
@@ -193,6 +197,9 @@ BEGIN
                        write(my_line, string'(")"));
                        writeline(output, my_line);
                end if;
+
+               delay_access_r <= delay_access_s;
+               delay_access_r2 <= delay_access_r;
        end process;