return mcsrc;
}
+uint32_t pxmc_rocon_vin_adc_last;
+int pxmc_rocon_vin_act;
+int pxmc_rocon_vin_ofs = 20978;
+int pxmc_rocon_vin_mul = 32905;
+int pxmc_rocon_vin_shr = 14;
+
+static inline
+void pxmc_rocon_vin_compute(void)
+{
+ volatile uint32_t *vin_adc_reg;
+ uint32_t vin_adc;
+ int vin_act;
+
+ vin_adc_reg = fpga_lx_master_receiver_base;
+ vin_adc_reg += LX_MASTER_DATA_OFFS + 1 + 8 * 2;
+
+ vin_adc = *vin_adc_reg;
+
+ vin_act = (int16_t)(vin_adc - pxmc_rocon_vin_adc_last);
+ pxmc_rocon_vin_adc_last = vin_adc;
+
+ vin_act = (pxmc_rocon_vin_ofs - vin_act) * pxmc_rocon_vin_mul;
+ vin_act >>= pxmc_rocon_vin_shr;
+
+ pxmc_rocon_vin_act = vin_act;
+}
+
const uint8_t onesin10bits[1024]={
0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5,
1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5,2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6,
hal_gpio_set_value(T2MAT1_PIN, 0);
hal_gpio_set_value(T2MAT0_PIN, 0);
+ pxmc_rocon_vin_compute();
+
if (pxmc_rocon_rx_data_hist_buff >= pxmc_rocon_rx_data_hist_buff_end)
pxmc_rocon_rx_data_hist_buff = NULL;