RoCoN: added support and test command to capture LXPWR ADC stream.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>

diff --git a/sw/app/rocon/appl_tests.c b/sw/app/rocon/appl_tests.c
index 2e559d1715e66cecf08d585b4f00e808620397c7..9406cecf334ca5999f75cbe836391e52be0e79f6 100644 (file)
--- a/sw/app/rocon/appl_tests.c
+++ b/sw/app/rocon/appl_tests.c
@@ -10,12 +10,14 @@
 #include <hal_gpio.h>
 #include <hal_machperiph.h>
 #include <LPC17xx.h>
+#include <lpcTIM.h>
 #include <spi_drv.h>
 
 #include <ul_log.h>
 #include <ul_logreg.h>
 
 #include "appl_defs.h"
+#include "appl_fpga.h"
 
 int cmd_do_test_memusage(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
 {
@@ -271,6 +273,91 @@ int cmd_do_testsdram(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
 }
 #endif /*SDRAM_BASE*/
 
+#define LXPWR_RX_TIM  LPC_TIM2
+#define LXPWR_RX_IRQn TIMER2_IRQn
+
+volatile void *lxpwr_rx_data_hist_buff;
+volatile void *lxpwr_rx_data_hist_buff_end;
+
+IRQ_HANDLER_FNC(lxpwr_rx_done_isr)
+{
+  uint32_t ir;
+
+  ir = LXPWR_RX_TIM->IR & LPC_TIM_IR_ALL_m;
+  LXPWR_RX_TIM->IR = ir;
+  if (ir & LPC_TIM_IR_CR1INT_m) {
+    uint32_t cr0, cr1;
+    cr0 = LXPWR_RX_TIM->CR0;
+    cr1 = LXPWR_RX_TIM->CR1;
+
+    hal_gpio_set_value(T2MAT0_PIN, 1);
+    hal_gpio_set_value(T2MAT1_PIN, 0);
+    hal_gpio_set_value(T2MAT0_PIN, 0);
+
+    if (lxpwr_rx_data_hist_buff >= lxpwr_rx_data_hist_buff_end)
+      lxpwr_rx_data_hist_buff = NULL;
+
+    if (lxpwr_rx_data_hist_buff != NULL) {
+      int i;
+      volatile uint32_t *rec_reg = fpga_lx_master_receiver_base + 8;
+      uint16_t *pbuf = (uint16_t *)lxpwr_rx_data_hist_buff;
+      for (i = 0; i < 16; i++) {
+        *(pbuf++) = *(rec_reg++);
+      }
+      lxpwr_rx_data_hist_buff = pbuf;
+    }
+  }
+
+  return IRQ_HANDLED;
+}
+
+int lxpwr_rx_done_isr_init(void)
+{
+
+  disable_irq(LXPWR_RX_IRQn);
+
+  hal_pin_conf_set(T2MAT0_PIN, PORT_CONF_GPIO_OUT_LO);
+  hal_pin_conf_set(T2MAT1_PIN, PORT_CONF_GPIO_OUT_LO);
+  hal_pin_conf(T2CAP0_PIN);
+  hal_pin_conf(T2CAP1_PIN);
+
+  hal_gpio_direction_output(T2MAT0_PIN, 1);
+  hal_gpio_direction_output(T2MAT1_PIN, 0);
+  hal_gpio_set_value(T2MAT0_PIN, 0);
+
+  /* Enable CLKOUT pin function, source CCLK, divide by 1 */
+  LPC_SC->CLKOUTCFG = 0x0100;
+
+  request_irq(LXPWR_RX_IRQn, lxpwr_rx_done_isr, 0, NULL,NULL);
+
+  LXPWR_RX_TIM->TCR = 0;
+  LXPWR_RX_TIM->CTCR = 0;
+  LXPWR_RX_TIM->PR = 0;        /* Divide by 1 */
+
+  LXPWR_RX_TIM->CCR = LPC_TIM_CCR_CAP0RE_m | LPC_TIM_CCR_CAP1FE_m |
+                   LPC_TIM_CCR_CAP1I_m;
+
+  LXPWR_RX_TIM->EMR = __val2mfld(LPC_TIM_EMR_EMC0_m, LPC_TIM_EMR_NOP) |
+                   __val2mfld(LPC_TIM_EMR_EMC1_m, LPC_TIM_EMR_NOP);
+
+  LXPWR_RX_TIM->MCR = 0;                       /* No IRQ on MRx */
+  LXPWR_RX_TIM->TCR = LPC_TIM_TCR_CEN_m;       /* Enable timer counting */
+  enable_irq(LXPWR_RX_IRQn);           /* Enable interrupt */
+
+  return 0;
+
+}
+
+int cmd_do_testlxpwrrx(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+  lxpwr_rx_data_hist_buff = NULL;
+  lxpwr_rx_done_isr_init();
+  lxpwr_rx_data_hist_buff_end = (void *)(FPGA_CONFIGURATION_FILE_ADDRESS +
+                                         0x80000);
+  lxpwr_rx_data_hist_buff = (void *)FPGA_CONFIGURATION_FILE_ADDRESS;
+  return 0;
+}
+
 cmd_des_t const cmd_des_test_memusage = {0, 0,
                 "memusage", "report memory usage", cmd_do_test_memusage,
 {
@@ -327,6 +414,12 @@ cmd_des_t const cmd_des_testsdram = {0, 0,
                                     };
 #endif /*SDRAM_BASE*/
 
+
+cmd_des_t const cmd_des_testlxpwrrx = {0, 0,
+                                     "testlxpwrrx", "capture data stream from lxpwr",
+                                     cmd_do_testlxpwrrx, {(void *)0}
+                                    };
+
 cmd_des_t const *const cmd_appl_tests[] =
 {
   &cmd_des_test_memusage,
@@ -341,5 +434,6 @@ cmd_des_t const *const cmd_appl_tests[] =
 #ifdef SDRAM_BASE
   &cmd_des_testsdram,
 #endif /*SDRAM_BASE*/
+  &cmd_des_testlxpwrrx,
   NULL
 };