volatile uint32_t *fpga_lx_master_transmitter_cycle = (volatile uint32_t *)FPGA_LX_MASTER_TRANSMITTER_CYCLE;
volatile uint32_t *fpga_lx_master_receiver_base = (volatile uint32_t *)FPGA_LX_MASTER_RECEIVER_BASE;
volatile uint32_t *fpga_lx_master_receiver_reg = (volatile uint32_t *)FPGA_LX_MASTER_RECEIVER_REG;
+volatile uint32_t *fpga_lx_master_receiver_done_div = (volatile uint32_t *)FPGA_LX_MASTER_RECEIVER_DONE_DIV;
volatile uint32_t *fpga_lx_master_reset = (volatile uint32_t *)FPGA_LX_MASTER_RESET;
volatile uint32_t *fpga_lx_master_conf = (volatile uint32_t *)FPGA_CONFIGURATION_FILE_ADDRESS;
#define FPGA_LX_MASTER_TRANSMITTER_WDOG 0x80025008
#define FPGA_LX_MASTER_TRANSMITTER_CYCLE 0x8002500C
#define FPGA_LX_MASTER_RECEIVER_REG 0x80025010
+#define FPGA_LX_MASTER_RECEIVER_DONE_DIV 0x80025014
extern volatile uint32_t *fpga_lx_master_transmitter_base;
extern volatile uint32_t *fpga_lx_master_transmitter_reg;
extern volatile uint32_t *fpga_lx_master_transmitter_control_reg;
extern volatile uint32_t *fpga_lx_master_receiver_control_reg;
+extern volatile uint32_t *fpga_lx_master_receiver_done_div;
#define FPGA_LX_MASTER_CONTROL_ADDRESS_MASK 0x0000FF00
#define FPGA_LX_MASTER_CONTROL_DATA_LENGTH_MASK 0x000000FF
*fpga_lx_master_reset = 1;
*fpga_lx_master_transmitter_reg = 0;
*fpga_lx_master_transmitter_cycle = 2500; /* 50 MHz -> 20 kHz */
+ *fpga_lx_master_receiver_done_div = 1 << 8;
for (i = 0; i < LX_MASTER_DATA_OFFS + lxpwr_words * lxpwr_chips; i++)
fpga_lx_master_receiver_base[i] = 0;
fpga_lx_master_transmitter_base[grp_out++] = 0x0000;
*fpga_lx_master_reset = 0;
+ *fpga_lx_master_transmitter_cycle = 2500; /* 50 MHz -> 20 kHz */
+ *fpga_lx_master_receiver_done_div = 1 << 8;
return 0;
}