]> rtime.felk.cvut.cz Git - fpga/lx-cpu1/lx-rocon.git/commitdiff
RoCoN: FPGA register for Rx event reduction ration configuration.
authorPavel Pisa <ppisa@pikron.com>
Sun, 23 Nov 2014 15:16:06 +0000 (16:16 +0100)
committerPavel Pisa <ppisa@pikron.com>
Sun, 23 Nov 2014 15:16:06 +0000 (16:16 +0100)
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
sw/app/rocon/appl_fpga.c
sw/app/rocon/appl_fpga.h
sw/app/rocon/appl_pxmc.c

index cfd136dc26a306a42ec298ea5f4c1ce200b79ad6..a0db72db33121e4694511b2cd351ff1d41f9d57d 100644 (file)
@@ -65,6 +65,7 @@ volatile uint32_t *fpga_lx_master_transmitter_wdog = (volatile uint32_t *)FPGA_L
 volatile uint32_t *fpga_lx_master_transmitter_cycle = (volatile uint32_t *)FPGA_LX_MASTER_TRANSMITTER_CYCLE;
 volatile uint32_t *fpga_lx_master_receiver_base = (volatile uint32_t *)FPGA_LX_MASTER_RECEIVER_BASE;
 volatile uint32_t *fpga_lx_master_receiver_reg = (volatile uint32_t *)FPGA_LX_MASTER_RECEIVER_REG;
+volatile uint32_t *fpga_lx_master_receiver_done_div = (volatile uint32_t *)FPGA_LX_MASTER_RECEIVER_DONE_DIV;
 volatile uint32_t *fpga_lx_master_reset = (volatile uint32_t *)FPGA_LX_MASTER_RESET;
 volatile uint32_t *fpga_lx_master_conf  = (volatile uint32_t *)FPGA_CONFIGURATION_FILE_ADDRESS;
 
index b3371efbb44d2fec7b9076b4fe6bcb58279bc1cf..ad66654ba8ed0f0c69f7fb3f00e157bf2f709008 100644 (file)
@@ -91,6 +91,7 @@ extern volatile uint8_t *fpga_irc_reset;
 #define FPGA_LX_MASTER_TRANSMITTER_WDOG   0x80025008
 #define FPGA_LX_MASTER_TRANSMITTER_CYCLE  0x8002500C
 #define FPGA_LX_MASTER_RECEIVER_REG       0x80025010
+#define FPGA_LX_MASTER_RECEIVER_DONE_DIV  0x80025014
 
 extern volatile uint32_t *fpga_lx_master_transmitter_base;
 extern volatile uint32_t *fpga_lx_master_transmitter_reg;
@@ -103,6 +104,7 @@ extern volatile uint32_t *fpga_lx_master_conf;
 
 extern volatile uint32_t *fpga_lx_master_transmitter_control_reg;
 extern volatile uint32_t *fpga_lx_master_receiver_control_reg;
+extern volatile uint32_t *fpga_lx_master_receiver_done_div;
 
 #define FPGA_LX_MASTER_CONTROL_ADDRESS_MASK     0x0000FF00
 #define FPGA_LX_MASTER_CONTROL_DATA_LENGTH_MASK 0x000000FF
index b5e06c75fd09fef41c1e9812950758ac6048ece5..7fc9fea6149d583b8556857f1f56fb718f60fa30 100644 (file)
@@ -726,6 +726,7 @@ pxmc_rocon_pwm_master_init(void)
   *fpga_lx_master_reset = 1;
   *fpga_lx_master_transmitter_reg = 0;
   *fpga_lx_master_transmitter_cycle = 2500; /* 50 MHz -> 20 kHz */
+  *fpga_lx_master_receiver_done_div = 1 << 8;
 
   for (i = 0; i < LX_MASTER_DATA_OFFS + lxpwr_words * lxpwr_chips; i++)
     fpga_lx_master_receiver_base[i] = 0;
@@ -752,6 +753,8 @@ pxmc_rocon_pwm_master_init(void)
   fpga_lx_master_transmitter_base[grp_out++] = 0x0000;
 
   *fpga_lx_master_reset = 0;
+  *fpga_lx_master_transmitter_cycle = 2500; /* 50 MHz -> 20 kHz */
+  *fpga_lx_master_receiver_done_div = 1 << 8;
 
   return 0;
 }