RoCoN: Change hard-coded IRC status bit positions to named bit masks.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>

diff --git a/sw/app/rocon/appl_pxmc.c b/sw/app/rocon/appl_pxmc.c
index f6c2e4fe852dd3b12c1e87580af2cea6a3b9e693..ec8478ecc847cfe4cd4061fa430fe8ce6f1f6ddc 100644 (file)
--- a/sw/app/rocon/appl_pxmc.c
+++ b/sw/app/rocon/appl_pxmc.c
@@ -26,6 +26,7 @@
 #include <hal_gpio.h>
 #include <hal_machperiph.h>
 #include <stdlib.h>
+#include <string.h>
 
 #include "appl_defs.h"
 #include "appl_fpga.h"
@@ -118,7 +119,8 @@ pxmc_inp_rocon_is_mark(pxmc_state_t *mcs)
 
   irc_state = *fpga_irc_state[chan];
 
-  mark = (irc_state ^ (mcs->pxms_cfg >> PXMS_CFG_HPS_b)) & 1;
+  mark = ((irc_state >> (ffs(FPGA_IRC_STATE_MARK_MASK) - 1)) ^
+         (mcs->pxms_cfg >> PXMS_CFG_HPS_b)) & 1;
 
   filt = pxmc_rocon_mark_filt[chan];
   filt = (filt << 1) | mark;
@@ -135,9 +137,9 @@ pxmc_inp_rocon_is_index_edge(pxmc_state_t *mcs)
   int chan=mcs->pxms_inp_info;
 
   irc_state = *fpga_irc_state[chan];
-  *fpga_irc_state[chan] = 1 << 2;
+  *fpga_irc_state[chan] = FPGA_IRC_STATE_INDEX_EVENT_MASK;
 
-  index = (irc_state >> 2) & 1;
+  index = (irc_state >> (ffs(FPGA_IRC_STATE_INDEX_EVENT_MASK) - 1)) & 1;
 
   return index;
 }
@@ -206,7 +208,7 @@ pxmc_inp_rocon_ptofs_from_index_poll(struct pxmc_state *mcs, int diff2err)
   long irc;
   long index_irc;
 
-  if (!(*fpga_irc_state[chan] & (1 << 2)))
+  if (!(*fpga_irc_state[chan] & FPGA_IRC_STATE_INDEX_EVENT_MASK))
     return 0;
 
   irc = fpga_irc[chan]->count + pxmc_rocon_irc_offset[chan];
@@ -1587,7 +1589,7 @@ int pxmc_initialize(void)
   for (i = 0; i < 8; i++) {
     fpga_irc[i]->count = 0;
     fpga_irc[i]->count_index = 0;
-    *fpga_irc_state[i] = 1 << 2;
+    *fpga_irc_state[i] = FPGA_IRC_STATE_INDEX_EVENT_MASK;
   }
 
   /* Initialize QEI module for IRC counting */