Update Tumbl and test of concurrent access.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>

diff --git a/hw/tb/lx_tumbl_tb.vhd b/hw/tb/lx_tumbl_tb.vhd
index 8c59fe8e7f3c954ae918f7e646d8cee3a8598711..dccefe1aa66385a044187cd0bfd1ecad34e35b89 100644 (file)
--- a/hw/tb/lx_tumbl_tb.vhd
+++ b/hw/tb/lx_tumbl_tb.vhd
@@ -146,15 +146,35 @@ BEGIN
 
        end process;
 
-       events_process: process(cycle_cnt, xmemb_sel_s, delay_access_r, delay_access_r2)
+       --events_process: process(cycle_cnt, xmemb_sel_s, delay_access_r, delay_access_r2)
+       --begin
+       --      -- Simulate externall access to xmem bus shared with Tumbl
+       --      if cycle_cnt >= 46 and cycle_cnt <= 47 then
+       --      -- if xmemb_sel_s = '1' and (delay_access_r = '0' or delay_access_r2 = '0') then
+       --              delay_access_s <= '1';
+       --      else
+       --              delay_access_s <= '0';
+       --      end if;
+       --end process;
+
+       events_process: process
        begin
-               -- Simulate externall access to xmem bus shared with Tumbl
-               if cycle_cnt >= 33 and cycle_cnt <= 33 then
-               -- if xmemb_sel_s = '1' and (delay_access_r = '0' or delay_access_r2 = '0') then
-                       delay_access_s <= '1';
-               else
-                       delay_access_s <= '0';
-               end if;
+
+               wait until clk_cpu'event and clk_cpu = '1' and imem_ready_s = '1';
+
+               -- Simulate external master accesses to Tumbl shared xmem bus
+               xmem_loop: loop
+                       wait until clk_cpu'event and clk_cpu = '1';
+                       wait until clk_cpu'event and clk_cpu = '1';
+                       wait until clk_cpu'event and clk_cpu = '1';
+                       wait until clk_cpu'event and clk_cpu = '1';
+                       wait until clk_cpu'event and clk_cpu = '1';
+                       delay_access_s <= transport '1' after 2 ns;
+                       wait until clk_cpu'event and clk_cpu = '1';
+                       wait until clk_cpu'event and clk_cpu = '1';
+                       delay_access_s <= transport '0' after 2 ns;
+               end loop xmem_loop;
+
        end process;
 
        -- Enable xmem clken only when bus available for Tumbl

diff --git a/submodule/tumbl b/submodule/tumbl
index 3d80b5ce3a1537adda4bf6be12d6d7d94a9cc27c..0e360bb03b9126943802fc74133e0e022bed48bf 160000 (submodule)
--- a/submodule/tumbl
+++ b/submodule/tumbl
@@ -1 +1 @@
-Subproject commit 3d80b5ce3a1537adda4bf6be12d6d7d94a9cc27c
+Subproject commit 0e360bb03b9126943802fc74133e0e022bed48bf