Tumbl: Separate wait for external bus data and state when external bus is taken by...

Tumbl: Separate wait for external bus data and state when external bus is taken by other master.

Original design reuses external bus clock enable/ready indication
for external master wait. This solution is broken because
external master leaves other data on the bus when clocks
are re-enabled than Tumbl expects. When external master
requests bus at/after end of the Tumbl external memory cycle
there is no need to do anything special in such case.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>