Report detailed analysis of timing problems for 20 worst signal traces.

[fpga/lx-cpu1/lx-rocon.git] / hw / Makefile

diff --git a/hw/Makefile b/hw/Makefile
index f507bd103783e6ebe05ae9fdc7525e68d51fb7ae..882628de2c9d915ded9309acd30e3938e6763666 100644 (file)
--- a/hw/Makefile
+++ b/hw/Makefile
@@ -47,6 +47,8 @@ NCD_MAP        := $(OUTB)_map.ncd
 NCD            := $(OUTB).ncd
 BIN            := $(OUTB).bin
 PKG            := $(OUTB).pkg
+TWR            := $(OUTB).twr
+TSI            := $(OUTB).tsi
 
 REQ_NGC            := $(REQB).ngc
 REQ_NGD            := $(REQB).ngd
@@ -189,6 +191,8 @@ re-map $(REQ_NCD_MAP) $(REQ_PCF): $(REQ_NGD)
 re-par $(REQ_NCD): $(REQ_NCD_MAP) $(REQ_PCF)
        cd $(OUT); \
        par -w -intstyle $(INTSTYLE) -ol high -xe n -mt off $(NCD_MAP) $(NCD) $(PCF) | tee par.log
+       cd $(OUT); \
+       trce -e 20 -tsi $(TSI) -o $(TWR) $(NCD) $(PCF)
 
 .PHONY: re-gen
 re-gen $(REQ_BIN): $(REQ_NCD)