]> rtime.felk.cvut.cz Git - fpga/lx-cpu1/lx-rocon.git/blobdiff - hw/dff2.vhd
RoCoN: USB CDC ACM use maximal packet length - 64 bytes.
[fpga/lx-cpu1/lx-rocon.git] / hw / dff2.vhd
index 28d92b4d137b42b8bcbd85c33340f05764aea0c0..a3d3c07a9d12caeb08ac261b5a129f3852161cd3 100644 (file)
@@ -3,39 +3,42 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 use ieee.numeric_std.all;
+use work.lx_rocon_pkg.all;
 
 -- D circuit (filtered)
 
 entity dff2 is
   port
        (
-    clk   : in std_logic;
-               reset : in std_logic;
-    d     : in std_logic;
-    q     : out std_logic
+    clk_i   : in std_logic;
+    d_i     : in std_logic;
+    q_o     : out std_logic
   );
 end dff2;
 
 architecture behavioral of dff2 is
-       signal last_d : std_logic;
-  signal data: std_logic;
+       signal d_2r   : std_logic;
+       signal d_r    : std_logic;
+  signal data_s : std_logic;
+
+       -- XST attributes
+  attribute REGISTER_DUPLICATION : string;
+       attribute REGISTER_DUPLICATION of d_2r : signal is "NO";
+       attribute REGISTER_DUPLICATION of d_r  : signal is "NO";
+
 begin
-  q <= data;
-
-  seq: process(clk)
-  begin
-    if clk = '1' and clk'event then
-                       if reset = '1' then
-                               last_d <= '0';
-                               data <= '0';
-                       else
-                               if d = last_d then
-                                       data <= d;
-                               end if;
-                       end if;
-
-                       last_d <= d;
+  q_o <= data_s;
+
+seq:
+       process
+       begin
+    wait until clk_i'event and clk_i = '1';
+               if d_2r = d_r then
+                       data_s <= d_r;
                end if;
+
+               d_2r    <= d_r;
+               d_r     <= d_i;
   end process;
 
 end behavioral;