Update FPGA, fix hazard conditions in BRAM

[fpga/lx-cpu1/lx-rocon.git] / hw / lx_rocon_pkg.vhd

diff --git a/hw/lx_rocon_pkg.vhd b/hw/lx_rocon_pkg.vhd
index 50ba1a43b39928492b2862a915abc3bccced6331..f81465295c1d673a5baacb91b30f30b594433d2a 100644 (file)
--- a/hw/lx_rocon_pkg.vhd
+++ b/hw/lx_rocon_pkg.vhd
@@ -126,23 +126,21 @@ package lx_rocon_pkg is
   );
        end component;
 
-       -- D sampler (filtered)
+       -- D sampler (filtered, 2 cycles)
        component dff2
        port
        (
     clk_i   : in std_logic;
-               reset_i : in std_logic;
     d_i     : in std_logic;
     q_o     : out std_logic
   );
   end component;
 
-       -- D sampler (filtered)
+       -- D sampler (filtered, 3 cycles)
        component dff3
        port
        (
     clk_i   : in std_logic;
-               reset_i : in std_logic;
     d_i     : in std_logic;
     q_o     : out std_logic
   );
@@ -428,39 +426,16 @@ package lx_rocon_pkg is
        --------------------------------------------------------------------------------
        -- BRAM
        --------------------------------------------------------------------------------
+       type BRAM_type is (READ_FIRST, WRITE_FIRST, NO_CHANGE);
 
-       component xilinx_dualport_bram_write_first
-       generic
-       (
-               byte_width    : positive := 8;
-               address_width : positive := 8;
-               we_width      : positive := 4
-       );
-       port
-       (
-               clka  : in std_logic;
-               rsta  : in std_logic;
-               ena   : in std_logic;
-               wea   : in std_logic_vector((we_width-1) downto 0);
-               addra : in std_logic_vector((address_width-1) downto 0);
-               dina  : in std_logic_vector(((byte_width*we_width)-1) downto 0);
-               douta : out std_logic_vector(((byte_width*we_width)-1) downto 0);
-               clkb  : in std_logic;
-               rstb  : in std_logic;
-               enb   : in std_logic;
-               web   : in std_logic_vector((we_width-1) downto 0);
-               addrb : in std_logic_vector((address_width-1) downto 0);
-               dinb  : in std_logic_vector(((byte_width*we_width)-1) downto 0);
-               doutb : out std_logic_vector(((byte_width*we_width)-1) downto 0)
-       );
-       end component;
-
-       component xilinx_dualport_bram_no_change
+       component xilinx_dualport_bram
        generic
        (
                byte_width    : positive := 8;
                address_width : positive := 8;
-               we_width      : positive := 4
+               we_width      : positive := 4;
+               port_a_type   : BRAM_type := READ_FIRST;
+               port_b_type   : BRAM_type := READ_FIRST
        );
        port
        (