Update FPGA, fix hazard conditions in BRAM

[fpga/lx-cpu1/lx-rocon.git] / hw / lx-rocon_tumbl / lx_rocon_dmem.vhd

diff --git a/hw/lx-rocon_tumbl/lx_rocon_dmem.vhd b/hw/lx-rocon_tumbl/lx_rocon_dmem.vhd
index cccc34e4d71ba26bc56f8ecd5080970bdbdd1a30..f414868f96622d35da2128a930385ad9c26dac96 100644 (file)
--- a/hw/lx-rocon_tumbl/lx_rocon_dmem.vhd
+++ b/hw/lx-rocon_tumbl/lx_rocon_dmem.vhd
@@ -33,12 +33,14 @@ end lx_rocon_dmem;
 architecture rtl of lx_rocon_dmem is
 begin
 
-I_RAMB: xilinx_dualport_bram_write_first
+I_RAMB: xilinx_dualport_bram
        generic map
        (
                we_width => 4,
                byte_width => 8,
-               address_width => 10
+               address_width => 10,
+               port_a_type => READ_FIRST,
+               port_b_type => READ_FIRST
        )
        port map
        (