Update FPGA, fix hazard conditions in BRAM

[fpga/lx-cpu1/lx-rocon.git] / hw / lx-rocon.ucf

diff --git a/hw/lx-rocon.ucf b/hw/lx-rocon.ucf
index 1ae08cefaeb87ab2ab51287fbdf0d64509d61df9..1a9776cc923eff4638d3ee31c8490e81f629359a 100644 (file)
--- a/hw/lx-rocon.ucf
+++ b/hw/lx-rocon.ucf
@@ -16,7 +16,7 @@ NET INIT                LOC = P39  | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
 
 # Memory peripheral
 NET CS0_XC              LOC = P64  | IOSTANDARD = LVCMOS33 | SLEW = FAST;
-#NET CS1_XC              LOC = P1   | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
+#NET CS1_XC              LOC = P1   | IOSTANDARD = LVCMOS33 | SLEW = FAST;
 
 NET RD                  LOC = P60  | IOSTANDARD = LVCMOS33 | SLEW = FAST;
 NET BLS<0>              LOC = P70  | IOSTANDARD = LVCMOS33 | SLEW = FAST;