Update FPGA, fix hazard conditions in BRAM

[fpga/lx-cpu1/lx-rocon.git] / hw / dff3.vhd

diff --git a/hw/dff3.vhd b/hw/dff3.vhd
index dee488f6c091d5044e6f2e8ded1dadcd9c1b648f..53914902d9194322afaf5c32aaaa220c2922a535 100644 (file)
--- a/hw/dff3.vhd
+++ b/hw/dff3.vhd
@@ -11,7 +11,6 @@ entity dff3 is
   port
        (
     clk_i   : in std_logic;
-               reset_i : in std_logic;
     d_i     : in std_logic;
     q_o     : out std_logic
   );
@@ -22,6 +21,13 @@ architecture behavioral of dff3 is
   signal d_2r   : std_logic;
        signal d_r    : std_logic;
   signal data_s : std_logic;
+
+       -- XST attributes
+  attribute REGISTER_DUPLICATION : string;
+       attribute REGISTER_DUPLICATION of d_3r : signal is "NO";
+       attribute REGISTER_DUPLICATION of d_2r : signal is "NO";
+       attribute REGISTER_DUPLICATION of d_r  : signal is "NO";
+
 begin
   q_o <= data_s;
 
@@ -29,12 +35,7 @@ seq:
        process
        begin
     wait until clk_i'event and clk_i = '1';
-               if reset_i = '1' then
-                       d_3r   <= '0';
-                       d_2r   <= '0';
-                       d_r    <= '0';
-                       data_s <= '0';
-               elsif d_3r = d_2r and d_2r = d_r then
+               if d_3r = d_2r and d_2r = d_r then
                        data_s <= d_3r;
                end if;