--
s1_clk_out : out std_logic;
s1_mosi : out std_logic;
- s1_sync_out : out std_logic
+ s1_sync_out : out std_logic;
+ -- signal connected to external JK FF
+ event_jk_j : out std_logic
);
end lx_rocon_top;
signal lxmaster_out_s : std_logic_vector(15 downto 0);
signal lxmaster_ce_s : std_logic;
signal lxmaster_next_ce_s : std_logic;
+ -- LX function approximation
+ signal lxfncapprox_out_s : std_logic_vector(31 downto 0);
+ signal lxfncapprox_ce_s : std_logic;
+ signal lxfncapprox_next_ce_s : std_logic;
-- Signals for external bus transmission
signal data_i_s : std_logic_vector(31 downto 0);
signal data_o_s : std_logic_vector(31 downto 0);
signal cs0_xc_f_s : std_logic;
signal rd_f_s : std_logic; -- Filtered RD
signal i_rd_s : std_logic; -- Internal bus RD (active 1)
- signal next_i_rd_s : std_logic;
+ -- signal next_i_rd_s : std_logic;
signal last_i_rd_s : std_logic; -- Delayed RD bus, used for latching
signal next_last_i_rd_s : std_logic;
signal i_rd_cycle2_s : std_logic; -- Some internal subsystems provide
signal tumbl_xmemb_o_s : CORE2DMEMB_Type;
signal tumbl_xmemb_i_s : DMEMB2CORE_Type;
signal tumbl_xmemb_sel_s : std_logic;
+ -- Interrupt event sources and processing
+ signal lxmaster_rx_done_s : std_logic;
+ signal lxmaster_rx_done_r : std_logic;
+ signal lxmaster_rx_done_last_s : std_logic;
+ signal lxmaster_rx_done_last_r : std_logic;
+
+ -- signal s0 : std_logic;
+ -- signal s1 : std_logic;
+ -- signal s2 : std_logic;
-- XST attributes
attribute REGISTER_DUPLICATION : string;
attribute REGISTER_DUPLICATION of address : signal is "NO";
attribute REGISTER_DUPLICATION of address_f_s : signal is "NO";
attribute REGISTER_DUPLICATION of cs0_xc : signal is "NO";
+ attribute REGISTER_DUPLICATION of cs0_xc_f_s : signal is "NO";
begin
data_o => lxmaster_out_s,
bls_i => tumbl_bls_s(1 downto 0),
--
+ rx_done_o => lxmaster_rx_done_s,
+ --
clock_i => s1_clk_in,
miso_i => s1_miso,
sync_i => s1_sync_in,
clock_o => s1_clk_out,
mosi_o => s1_mosi,
sync_o => s1_sync_out
+ --
+ -- clock_i => s0,
+ -- miso_i => s1,
+ -- sync_i => not s2,
+ --
+ -- clock_o => s0,
+ -- mosi_o => s1,
+ -- sync_o => s2
+ );
+
+ -- s1_clk_out <= s0;
+ -- s1_mosi <= s1;
+ -- s1_sync_out <= s2;
+
+
+function_approx: component lx_fncapprox
+ port map
+ (
+ reset_i => reset_s,
+ clk_i => clk_50m,
+ -- Data bus
+ address_i => tumbl_address_s(4 downto 0),
+ next_ce_i => lxfncapprox_next_ce_s,
+ data_i => tumbl_data_i_s,
+ data_o => lxfncapprox_out_s,
+ bls_i => tumbl_bls_s
);
-- Reset
--
tumbl_xmemb_i_s.int <= '0'; -- No interrupt
-- Enable clken only when available for Tumbl
- tumbl_xmemb_i_s.clken <= not master_tumbl_xmem_lock_s;
+ tumbl_xmemb_i_s.bus_taken <= master_tumbl_xmem_lock_s;
+ tumbl_xmemb_i_s.bus_wait <= '0';
+
-- Bus update
memory_bus_logic:
- process(cs0_xc_f_s, rd_f_s, last_rd_s, i_rd_s, i_rd_cycle2_s, last_i_rd_s,
+ process(cs0_xc_f_s, rd_f_s, last_rd_s, i_rd_cycle2_s, last_i_rd_s,
bls_f_s, last_bls_s, data_f_s, data_write_s,
data_o_s, data_read_s, last_address_s, address_f_s)
begin
-- Defaults
- next_i_rd_s <= '0';
next_i_rd_cycle2_s <= '0';
next_address_hold_s <= '0';
if rd_f_s = '1' then
-- Internal read
if last_rd_s = '0' or (last_address_s /= address_f_s) then
- next_i_rd_s <= '1';
+ i_rd_s <= '1';
next_i_rd_cycle2_s <= '1';
+ next_last_i_rd_s <= '1';
elsif i_rd_cycle2_s = '1' then -- FIXME it seems that some internal
- next_i_rd_s <= '1'; -- peripherals demands 2 cycles to read
+ i_rd_s <= '1'; -- peripherals demands 2 cycles to read
+ next_last_i_rd_s <= '1';
+ else
+ i_rd_s <= '0';
+ next_last_i_rd_s <= '0';
end if;
if last_i_rd_s = '1' then
-- -- Not reading, anything goes
-- data_read_s <= (others => 'X');
next_data_read_s <= data_read_s;
+ i_rd_s <= '0';
+ next_last_i_rd_s <= '0';
end if;
next_last_rd_s <= rd_f_s;
- next_last_i_rd_s <= i_rd_s;
-- Data for write are captured only when BLS signals are stable
if bls_f_s /= "0000" then
end if;
else
next_last_rd_s <= '0';
+ i_rd_s <= '0';
next_last_i_rd_s <= '0';
next_i_bls_s <= "0000";
last_bls_s <= next_last_bls_s;
last_rd_s <= next_last_rd_s;
i_bls_s <= next_i_bls_s;
- i_rd_s <= next_i_rd_s;
+ -- i_rd_s <= next_i_rd_s;
i_rd_cycle2_s <= next_i_rd_cycle2_s;
last_i_rd_s <= next_last_i_rd_s;
data_write_s <= next_data_write_s;
-- Just copy these to their desired next state
irc_proc_ce_s <= irc_proc_next_ce_s;
lxmaster_ce_s <= lxmaster_next_ce_s;
+ lxfncapprox_ce_s <= lxfncapprox_next_ce_s;
end process;
-- Defaults
irc_proc_next_ce_s <= '0';
lxmaster_next_ce_s <= '0';
+ lxfncapprox_next_ce_s <= '0';
master_tumbl_xmem_lock_s <= '0';
--
addr_v := (others => '0');
if sel_v = '1' then
-- IRC: 0x0800 - 0x081F (32-bit address)
+ -- LX FNC AP: 0x0C00 - 0x0C1F (32-bit address)
-- LX MASTER: 0x1000 - 0x17FF (32-bit address)
if addr_v(14 downto 5) = "0001000000" then
irc_proc_next_ce_s <= '1';
+ elsif addr_v(14 downto 5) = "0001100000" then
+ lxfncapprox_next_ce_s <= '1';
elsif addr_v(14 downto 11) = "0010" then
lxmaster_next_ce_s <= '1';
end if;
-- Inputs to Tumbl (enabling and address muxing)
tumbl_bus_i:
- process(irc_proc_ce_s, irc_proc_out_s, lxmaster_ce_s, lxmaster_out_s, tumbl_xmemb_i_s)
+ process(irc_proc_ce_s, irc_proc_out_s, lxmaster_ce_s, lxmaster_out_s,
+ lxfncapprox_ce_s, lxfncapprox_out_s, tumbl_xmemb_i_s)
begin
tumbl_xmemb_i_s.data <= (others => 'X');
elsif lxmaster_ce_s = '1' then
tumbl_xmemb_i_s.data(15 downto 0) <= lxmaster_out_s;
tumbl_xmemb_i_s.data(31 downto 16) <= (others => '0');
+ elsif lxfncapprox_ce_s = '1' then
+ tumbl_xmemb_i_s.data <= lxfncapprox_out_s;
end if;
master_tumbl_xmem_out_s <= tumbl_xmemb_i_s.data;
end process;
+events_logic:
+ process(lxmaster_rx_done_r, lxmaster_rx_done_last_r)
+ begin
+ event_jk_j <= lxmaster_rx_done_r or lxmaster_rx_done_last_r;
+ lxmaster_rx_done_last_s <= lxmaster_rx_done_r;
+ end process;
+
+events_update:
+ process
+ begin
+ wait until clk_50m = '1' and clk_50m'event;
+
+ lxmaster_rx_done_r <= lxmaster_rx_done_s;
+ lxmaster_rx_done_last_r <= lxmaster_rx_done_last_s;
+ end process;
+
end Behavioral;
projects / fpga / lx-cpu1 / lx-rocon.git / blobdiff