Provide direct pass-trough drive of i_rd_s from filtered rd_f_s.

[fpga/lx-cpu1/lx-rocon.git] / hw / lx_rocon_top.vhd

diff --git a/hw/lx_rocon_top.vhd b/hw/lx_rocon_top.vhd
index 1f5b1e0b95f216b4da0355a4fa2581dc29d4a834..8abd3a79f7824ea1432c2a349b1ac912ec656645 100644 (file)
--- a/hw/lx_rocon_top.vhd
+++ b/hw/lx_rocon_top.vhd
@@ -136,7 +136,7 @@ architecture Behavioral of lx_rocon_top is
        signal cs0_xc_f_s          : std_logic;
        signal rd_f_s              : std_logic; -- Filtered RD
        signal i_rd_s              : std_logic; -- Internal bus RD (active 1)
-       signal next_i_rd_s         : std_logic;
+       -- signal next_i_rd_s         : std_logic;
        signal last_i_rd_s         : std_logic; -- Delayed RD bus, used for latching
        signal next_last_i_rd_s    : std_logic;
        signal i_rd_cycle2_s       : std_logic; -- Some internal subsystems provide
@@ -317,12 +317,11 @@ dff_reset: dff2
 
 -- Bus update
 memory_bus_logic:
-       process(cs0_xc_f_s, rd_f_s, last_rd_s, i_rd_s, i_rd_cycle2_s, last_i_rd_s,
+       process(cs0_xc_f_s, rd_f_s, last_rd_s, i_rd_cycle2_s, last_i_rd_s,
                bls_f_s, last_bls_s, data_f_s, data_write_s,
                data_o_s, data_read_s, last_address_s, address_f_s)
        begin
                -- Defaults
-               next_i_rd_s  <= '0';
                next_i_rd_cycle2_s <= '0';
                next_address_hold_s <= '0';
 
@@ -333,10 +332,15 @@ memory_bus_logic:
                        if rd_f_s = '1' then
                                -- Internal read
                                if last_rd_s = '0' or (last_address_s /= address_f_s) then
-                                       next_i_rd_s <= '1';
+                                       i_rd_s <= '1';
                                        next_i_rd_cycle2_s <= '1';
+                                       next_last_i_rd_s  <= '1';
                                elsif i_rd_cycle2_s = '1' then    -- FIXME it seems that some internal
-                                       next_i_rd_s <= '1'; -- peripherals demands 2 cycles to read
+                                       i_rd_s <= '1';            -- peripherals demands 2 cycles to read
+                                       next_last_i_rd_s  <= '1';
+                               else
+                                       i_rd_s            <= '0';
+                                       next_last_i_rd_s  <= '0';
                                end if;
 
                                if last_i_rd_s = '1' then
@@ -349,10 +353,11 @@ memory_bus_logic:
                        --      -- Not reading, anything goes
                        --      data_read_s       <= (others => 'X');
                                next_data_read_s  <= data_read_s;
+                               i_rd_s            <= '0';
+                               next_last_i_rd_s  <= '0';
                        end if;
 
                        next_last_rd_s            <= rd_f_s;
-                       next_last_i_rd_s          <= i_rd_s;
 
                        -- Data for write are captured only when BLS signals are stable
                        if bls_f_s /= "0000" then
@@ -369,6 +374,7 @@ memory_bus_logic:
                        end if;
                else
                        next_last_rd_s <= '0';
+                       i_rd_s <= '0';
                        next_last_i_rd_s <= '0';
 
                        next_i_bls_s <= "0000";
@@ -419,7 +425,7 @@ memory_bus_update:
                last_bls_s     <= next_last_bls_s;
                last_rd_s      <= next_last_rd_s;
                i_bls_s        <= next_i_bls_s;
-               i_rd_s         <= next_i_rd_s;
+               -- i_rd_s         <= next_i_rd_s;
                i_rd_cycle2_s  <= next_i_rd_cycle2_s;
                last_i_rd_s    <= next_last_i_rd_s;
                data_write_s   <= next_data_write_s;