Major refactorization in hw

[fpga/lx-cpu1/lx-rocon.git] / hw / calibration_write_register.vhd

diff --git a/hw/calibration_write_register.vhd b/hw/calibration_write_register.vhd
index 4dd7330e397ea9202a112ee6bb6f68ae7addd914..33922fbafc58a7963fc3ad7b2d3b9254912f0120 100644 (file)
--- a/hw/calibration_write_register.vhd
+++ b/hw/calibration_write_register.vhd
@@ -11,72 +11,59 @@ entity calibration_write_register is
        port
        (
                -- Clock
-               clk         : in std_logic;
-
+               clk_i   : in std_logic;
                -- Reset
-               reset       : in std_logic;
-
+               reset_i : in std_logic;
                -- Chip enable
-               ce          : in std_logic;
-
+               ce_i    : in std_logic;
                -- Data bus
-               data_in     : in std_logic_vector(31 downto 0);
-               data_out    : out std_logic_vector(31 downto 0);
-
+               data_i  : in std_logic_vector(31 downto 0);
+               data_o  : out std_logic_vector(31 downto 0);
                -- Bus signals
-               rd          : in std_logic;
-               bls         : in std_logic_vector(3 downto 0);
-               ta          : out std_logic
+               rd_i    : in std_logic;
+               bls_i   : in std_logic_vector(3 downto 0);
+               ta_o    : out std_logic
        );
 end calibration_write_register;
 
 architecture Behavioral of calibration_write_register is
-       signal value : std_logic_vector(31 downto 0);
+       signal value_s : std_logic_vector(31 downto 0);
 begin
 
        -- Read is immideate
-       memory_bus_read: process(rd, value)
+       memory_bus_read: process(rd_i, value_s)
        begin
-
-               ta <= rd;
-               data_out <= value;
-
+               ta_o   <= rd_i;
+               data_o <= value_s;
        end process;
 
        -- Write waits for clock
-       memory_bus_write: process(clk)
+       memory_bus_write: process(clk_i)
        begin
 
-               if clk = '1' and clk'event then
+               if clk_i = '1' and clk_i'event then
 
-                       if reset = '1' then
-                               value <= (others => '0');
-                       end if;
+                       if reset_i = '1' then
+                               value_s <= (others => '0');
+                       else
 
-                       if ce = '0' then
+                               if ce_i = '1' and bls_i /= "0000" then
 
-                               if reset = '0' and bls /= "1111" then
-
-                                       if bls(0) = '0' then
-                                               value(7 downto 0) <= data_in(7 downto 0);
+                                       if bls_i(0) = '1' then
+                                               value_s(7 downto 0)   <= data_i(7 downto 0);
                                        end if;
-
-                                       if bls(1) = '0' then
-                                               value(15 downto 8) <= data_in(15 downto 8);
+                                       if bls_i(1) = '1' then
+                                               value_s(15 downto 8)  <= data_i(15 downto 8);
                                        end if;
-
-                                       if bls(2) = '0' then
-                                               value(23 downto 16) <= data_in(23 downto 16);
+                                       if bls_i(2) = '1' then
+                                               value_s(23 downto 16) <= data_i(23 downto 16);
                                        end if;
-
-                                       if bls(3) = '0' then
-                                               value(31 downto 24) <= data_in(31 downto 24);
+                                       if bls_i(3) = '1' then
+                                               value_s(31 downto 24) <= data_i(31 downto 24);
                                        end if;
 
                                end if;
-
                        end if;
-
                end if;
 
        end process;