]> rtime.felk.cvut.cz Git - fpga/lx-cpu1/lx-rocon.git/blobdiff - hw/lx_rocon_top.vhd
Prevent register duplications of FPGA chipselect - cs0_xc_f_s - signal.
[fpga/lx-cpu1/lx-rocon.git] / hw / lx_rocon_top.vhd
index 8abd3a79f7824ea1432c2a349b1ac912ec656645..439d275615b2b3ec87824eed9304e4dee27df607 100644 (file)
@@ -85,7 +85,9 @@ entity lx_rocon_top is
                --
                s1_clk_out  : out std_logic;
                s1_mosi     : out std_logic;
-               s1_sync_out : out std_logic
+               s1_sync_out : out std_logic;
+               -- signal connected to external JK FF
+               event_jk_j  : out std_logic
        );
 end lx_rocon_top;
 
@@ -113,6 +115,10 @@ architecture Behavioral of lx_rocon_top is
        signal lxmaster_out_s           : std_logic_vector(15 downto 0);
        signal lxmaster_ce_s            : std_logic;
        signal lxmaster_next_ce_s       : std_logic;
+       -- LX function approximation
+       signal lxfncapprox_out_s        : std_logic_vector(31 downto 0);
+       signal lxfncapprox_ce_s         : std_logic;
+       signal lxfncapprox_next_ce_s    : std_logic;
        -- Signals for external bus transmission
        signal data_i_s                 : std_logic_vector(31 downto 0);
        signal data_o_s                 : std_logic_vector(31 downto 0);
@@ -165,6 +171,15 @@ architecture Behavioral of lx_rocon_top is
        signal tumbl_xmemb_o_s     : CORE2DMEMB_Type;
        signal tumbl_xmemb_i_s     : DMEMB2CORE_Type;
        signal tumbl_xmemb_sel_s   : std_logic;
+       -- Interrupt event sources and processing
+       signal lxmaster_rx_done_s  : std_logic;
+       signal lxmaster_rx_done_r  : std_logic;
+       signal lxmaster_rx_done_last_s : std_logic;
+       signal lxmaster_rx_done_last_r : std_logic;
+
+       -- signal s0   : std_logic;
+       -- signal s1   : std_logic;
+       -- signal s2   : std_logic;
 
        -- XST attributes
        attribute REGISTER_DUPLICATION : string;
@@ -175,6 +190,7 @@ architecture Behavioral of lx_rocon_top is
        attribute REGISTER_DUPLICATION of address : signal is "NO";
        attribute REGISTER_DUPLICATION of address_f_s : signal is "NO";
        attribute REGISTER_DUPLICATION of cs0_xc : signal is "NO";
+       attribute REGISTER_DUPLICATION of cs0_xc_f_s : signal is "NO";
 
 begin
 
@@ -275,6 +291,8 @@ memory_bus_lxmaster: bus_lxmaster
                data_o         => lxmaster_out_s,
                bls_i          => tumbl_bls_s(1 downto 0),
                --
+               rx_done_o      => lxmaster_rx_done_s,
+               --
                clock_i        => s1_clk_in,
                miso_i         => s1_miso,
                sync_i         => s1_sync_in,
@@ -282,6 +300,32 @@ memory_bus_lxmaster: bus_lxmaster
                clock_o        => s1_clk_out,
                mosi_o         => s1_mosi,
                sync_o         => s1_sync_out
+               --
+               -- clock_i        => s0,
+               -- miso_i         => s1,
+               -- sync_i         => not s2,
+               --
+               -- clock_o        => s0,
+               -- mosi_o         => s1,
+               -- sync_o         => s2
+       );
+
+       -- s1_clk_out      <= s0;
+       -- s1_mosi         <= s1;
+       -- s1_sync_out     <= s2;
+
+
+function_approx: component lx_fncapprox
+       port map
+       (
+               reset_i      => reset_s,
+               clk_i        => clk_50m,
+               -- Data bus
+               address_i      => tumbl_address_s(4 downto 0),
+               next_ce_i      => lxfncapprox_next_ce_s,
+               data_i         => tumbl_data_i_s,
+               data_o         => lxfncapprox_out_s,
+               bls_i          => tumbl_bls_s
        );
 
 -- Reset
@@ -312,7 +356,9 @@ dff_reset: dff2
        --
        tumbl_xmemb_i_s.int <= '0'; -- No interrupt
        -- Enable clken only when available for Tumbl
-       tumbl_xmemb_i_s.clken <= not master_tumbl_xmem_lock_s;
+       tumbl_xmemb_i_s.bus_taken <= master_tumbl_xmem_lock_s;
+       tumbl_xmemb_i_s.bus_wait <= '0';
+
 
 
 -- Bus update
@@ -439,6 +485,7 @@ memory_bus_update:
                -- Just copy these to their desired next state
                irc_proc_ce_s <= irc_proc_next_ce_s;
                lxmaster_ce_s <= lxmaster_next_ce_s;
+               lxfncapprox_ce_s <= lxfncapprox_next_ce_s;
 
        end process;
 
@@ -509,6 +556,7 @@ tumbl_bus_o:
                -- Defaults
                irc_proc_next_ce_s        <= '0';
                lxmaster_next_ce_s        <= '0';
+               lxfncapprox_next_ce_s     <= '0';
                master_tumbl_xmem_lock_s  <= '0';
                --
                addr_v                    := (others => '0');
@@ -527,9 +575,12 @@ tumbl_bus_o:
 
                if sel_v = '1' then
                        -- IRC:       0x0800 - 0x081F (32-bit address)
+                       -- LX FNC AP: 0x0C00 - 0x0C1F (32-bit address)
                        -- LX MASTER: 0x1000 - 0x17FF (32-bit address)
                        if addr_v(14 downto 5) = "0001000000" then
                                irc_proc_next_ce_s     <= '1';
+                       elsif addr_v(14 downto 5) = "0001100000" then
+                               lxfncapprox_next_ce_s  <= '1';
                        elsif addr_v(14 downto 11) = "0010" then
                                lxmaster_next_ce_s     <= '1';
                        end if;
@@ -539,7 +590,8 @@ tumbl_bus_o:
 
 -- Inputs to Tumbl (enabling and address muxing)
 tumbl_bus_i:
-       process(irc_proc_ce_s, irc_proc_out_s, lxmaster_ce_s, lxmaster_out_s, tumbl_xmemb_i_s)
+       process(irc_proc_ce_s, irc_proc_out_s, lxmaster_ce_s, lxmaster_out_s,
+               lxfncapprox_ce_s, lxfncapprox_out_s, tumbl_xmemb_i_s)
        begin
 
                tumbl_xmemb_i_s.data  <= (others => 'X');
@@ -552,11 +604,29 @@ tumbl_bus_i:
                elsif lxmaster_ce_s = '1' then
                        tumbl_xmemb_i_s.data(15 downto 0)  <= lxmaster_out_s;
                        tumbl_xmemb_i_s.data(31 downto 16) <= (others => '0');
+               elsif lxfncapprox_ce_s = '1' then
+                       tumbl_xmemb_i_s.data <= lxfncapprox_out_s;
                end if;
 
                master_tumbl_xmem_out_s <= tumbl_xmemb_i_s.data;
 
        end process;
 
+events_logic:
+       process(lxmaster_rx_done_r, lxmaster_rx_done_last_r)
+       begin
+               event_jk_j <= lxmaster_rx_done_r or lxmaster_rx_done_last_r;
+               lxmaster_rx_done_last_s <= lxmaster_rx_done_r;
+       end process;
+
+events_update:
+       process
+       begin
+               wait until clk_50m = '1' and clk_50m'event;
+
+               lxmaster_rx_done_r <= lxmaster_rx_done_s;
+               lxmaster_rx_done_last_r <= lxmaster_rx_done_last_s;
+       end process;
+
 end Behavioral;