Implemented initial version of LXPWR receiver FSM based on transmitter.

[fpga/lx-cpu1/lx-rocon.git] / hw / lx_rocon_top.vhd

diff --git a/hw/lx_rocon_top.vhd b/hw/lx_rocon_top.vhd
index 8abd3a79f7824ea1432c2a349b1ac912ec656645..cc99e404b3484dee3655201fb92f52d80cc72544 100644 (file)
--- a/hw/lx_rocon_top.vhd
+++ b/hw/lx_rocon_top.vhd
@@ -166,6 +166,10 @@ architecture Behavioral of lx_rocon_top is
        signal tumbl_xmemb_i_s     : DMEMB2CORE_Type;
        signal tumbl_xmemb_sel_s   : std_logic;
 
+       -- signal s0   : std_logic;
+       -- signal s1   : std_logic;
+       -- signal s2   : std_logic;
+
        -- XST attributes
        attribute REGISTER_DUPLICATION : string;
        attribute REGISTER_DUPLICATION of rd : signal is "NO";
@@ -282,8 +286,21 @@ memory_bus_lxmaster: bus_lxmaster
                clock_o        => s1_clk_out,
                mosi_o         => s1_mosi,
                sync_o         => s1_sync_out
+               --
+               -- clock_i        => s0,
+               -- miso_i         => s1,
+               -- sync_i         => not s2,
+               --
+               -- clock_o        => s0,
+               -- mosi_o         => s1,
+               -- sync_o         => s2
        );
 
+       -- s1_clk_out      <= s0;
+       -- s1_mosi         <= s1;
+       -- s1_sync_out     <= s2;
+
+
 -- Reset
 dff_reset: dff2
        port map