use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
+use work.lx_rocon_pkg.all;
-- D circuit (filtered)
port
(
clk_i : in std_logic;
- reset_i : in std_logic;
d_i : in std_logic;
q_o : out std_logic
);
end dff2;
architecture behavioral of dff2 is
- signal last_d_s : std_logic;
+ signal d_2r : std_logic;
+ signal d_r : std_logic;
signal data_s : std_logic;
+
+ -- XST attributes
+ attribute REGISTER_DUPLICATION : string;
+ attribute REGISTER_DUPLICATION of d_2r : signal is "NO";
+ attribute REGISTER_DUPLICATION of d_r : signal is "NO";
+
begin
q_o <= data_s;
seq:
- process(clk_i)
+ process
begin
- if clk_i = '1' and clk_i'event then
- if reset_i = '1' then
- last_d_s <= '0';
- data_s <= '0';
- else
- if d_i = last_d_s then
- data_s <= d_i;
- end if;
- end if;
-
- last_d_s <= d_i;
+ wait until clk_i'event and clk_i = '1';
+ if d_2r = d_r then
+ data_s <= d_r;
end if;
+
+ d_2r <= d_r;
+ d_r <= d_i;
end process;
end behavioral;