RoCoN: include optional mode parameter to testlxpwrrx command.

[fpga/lx-cpu1/lx-rocon.git] / sw / app / rocon / appl_tests.c

diff --git a/sw/app/rocon/appl_tests.c b/sw/app/rocon/appl_tests.c
index cf3a5f3582ab221dc4113025241491f3f7351114..7b1c8999ff6b72d35dc7a9de67098905769784ad 100644 (file)
--- a/sw/app/rocon/appl_tests.c
+++ b/sw/app/rocon/appl_tests.c
@@ -276,13 +276,31 @@ int cmd_do_testsdram(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
 
 int cmd_do_testlxpwrrx(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
 {
+  char *ps = param[1];
+  long mode = 0;
+  uint32_t *ptr;
+
+  if (ps != NULL) {
+    si_skspace(&ps);
+    if (*ps) {
+      if (si_ulong(&ps, &mode, 0) < 0)
+        return -CMDERR_BADPAR;
+    }
+  }
   pxmc_rocon_rx_data_hist_buff = NULL;
+  pxmc_rocon_rx_data_hist_mode = mode;
+
  #ifndef PXMC_ROCON_TIMED_BY_RX_DONE
   pxmc_rocon_rx_done_isr_setup(pxmc_rocon_rx_done_isr);
  #endif /*PXMC_ROCON_TIMED_BY_RX_DONE*/
   pxmc_rocon_rx_data_hist_buff_end = (void *)(FPGA_CONFIGURATION_FILE_ADDRESS +
                                          0x80000);
-  pxmc_rocon_rx_data_hist_buff = (void *)FPGA_CONFIGURATION_FILE_ADDRESS;
+  ptr = (void *)FPGA_CONFIGURATION_FILE_ADDRESS;
+  if (mode != 0) {
+    *(ptr++) = '10XL';
+    *(ptr++) = mode;
+  }
+  pxmc_rocon_rx_data_hist_buff = (void *)ptr;
   return 0;
 }